Datasheet

4 Dual-Core Intel
®
Xeon
®
Processor 7000 Series Datasheet
6.2.2 On-Demand Mode..................................................................................71
6.2.3 PROCHOT# Signal Pin .......................................................................... 71
6.2.4 FORCEPR# Signal Pin ..........................................................................72
6.2.5 THERMTRIP# Signal Pin .......................................................................72
6.2.6 Tcontrol and Fan Speed Reduction .......................................................72
6.2.7 Thermal Diode........................................................................................72
7 Features...........................................................................................................................73
7.1 Power-On Configuration Options ........................................................................ 73
7.2 Clock Control and Low Power States.................................................................. 73
7.2.1 Normal State ..........................................................................................73
7.2.2 HALT Power Down State .......................................................................74
7.2.3 Stop-Grant State ....................................................................................74
7.2.4 HALT/Grant Snoop State .......................................................................75
7.2.5 Enhanced HALT Powerdown State........................................................ 75
7.3 Enhanced Intel SpeedStep
®
Technology............................................................ 76
7.4 System Management Bus (SMBus) Interface .....................................................76
7.4.1 Processor Information ROM (PIROM)....................................................77
7.4.2 Scratch EEPROM ..................................................................................80
7.4.3 PIROM and Scratch EEPROM Supported SMBus Transactions...........80
7.4.4 SMBus Thermal Sensor .........................................................................81
7.4.5 Thermal Sensor Supported SMBus Transactions.................................. 81
7.4.6 SMBus Thermal Sensor Registers.........................................................84
7.4.7 SMBus Thermal Sensor Alert Interrupt ..................................................87
7.4.8 SMBus Device Addressing.....................................................................88
7.4.9 Managing Data in the PIROM ................................................................89
8 Boxed Processor Specifications.......................................................................................97
8.1 Introduction ......................................................................................................... 97
8.2 Mechanical Specifications................................................................................... 98
8.2.1 Boxed Processor Heatsink Dimensions ................................................. 98
8.2.2 Boxed Processor Heatsink Weight.......................................................104
8.2.3 Boxed Processor Retention Mechanism and Heatsink Supports.........104
8.3 Thermal Specifications......................................................................................105
8.3.1 Boxed Processor Cooling Requirements .............................................105
8.3.2 Boxed Processor Contents ..................................................................105
9 Debug Tools Specifications............................................................................................107
9.1 Logic Analyzer Interface (LAI)...........................................................................107
9.1.1 Mechanical Considerations ..................................................................107
9.1.2 Electrical Considerations......................................................................107