Datasheet

Register Description
54 Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 2
2.12.3 MC_DDR_THERM1_COMMAND0
MC_DDR_THERM1_COMMAND1
MC_DDR_THERM1_COMMAND2
This register contains the command portion of the DDR_THERM2# pin functionality (i.e.
what an assertion of the pin does).
2.12.4 MC_DDR_THERM0_STATUS0
MC_DDR_THERM0_STATUS1
MC_DDR_THERM0_STATUS2
This register contains the status portion of the DDR_THERM# pin functionality (that is,
what is happening or has happened with respect to the pin).
2RW0REF_2X. Force 2x refresh as long as DDR_THERM# is asserted (low).
1RW0DISABLE_EXTTS. Response to DDR_THERM# pin is disabled. ASSERTION and
DEASSERTION fields in the register MC_DDR_THERM0_STATUS are frozen.
0RW1S0LOCK. When set, all bits in this register are RO and cannot be written. Reset
will clear the lock.
Device: 4, 5, 6
Function: 3
Offset: 9Ch
Access as a Dword
Device: 4, 5, 6
Function: 3
Offset: A0h
Access as a Dword
Bit Type
Reset
Value
Description
3RW0THROTTLE. Force throttling when DDR_THERM# pin is asserted.
2RW0REF_2X. Force 2x refresh as long as DDR_THERM# is asserted (low).
1RW0DISABLE_EXTTS. Response to DDR_THERM# pin is disabled. ASSERTION and
DEASSERTION fields in the register MC_DDR_THERM_STATUS are frozen.
0RW1S0LOCK. When set, all bits in this register are RO and cannot be written. Reset
will clear the lock.
Device: 4, 5, 6
Function: 3
Offset: A4h
Access as a Dword
Bit Type
Reset
Value
Description
2RO0ASSERTION. An assertion edge was seen on DDR_THERM#. Write-1-to-clear.
1RO0DEASSERTION. A de-assertion edge was seen on DDR_THERM#. Write-1-to-
clear.
0RO0STATE. Present logical state of DDR_THERM# bit. This is a static indication of
the pin, and may be several clocks out of date due to the delay between the pin
and the signal.
STATE = 0 means DDR_THERM# is deasserted
STATE = 1 means DDR_THERM# is asserted