Datasheet

Register Description
52 Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 2
2.11.6 MC_CHANNEL_0_SCHEDULER_PARAMS
MC_CHANNEL_1_SCHEDULER_PARAMS
MC_CHANNEL_2_SCHEDULER_PARAMS
These are the parameters used to control parameters within the scheduler.
2.11.7 MC_CHANNEL_0_PAGETABLE_PARAMS2
MC_CHANNEL_1_PAGETABLE_PARAMS2
MC_CHANNEL_2_PAGETABLE_PARAMS2
These are the parameters used to control parameters for page closing policies.
Device: 4, 5, 6
Function: 0
Offset: 78h
Access as a Dword
Bit Type
Reset
Value
Description
14:5 RW 0 tRANKIDLE: Rank will go into powerdown after it has been idle for the
specified number of DCLKs. tRANKIDLE covers max(txxxPDEN). Minimum value
is tWRAPDEN. If CKE is being shared between ranks then both ranks must be
idle for this amount of time. A Power Down Entry command will be requested
for a rank after this number of DCLKs if no request to the rank is in the MC.
4:0 RW 0 tXP. Minimum delay from exit power down with DLL and any valid command.
Exit Precharge Power Down with DLL frozen to commands not requiring a
locked DLL.
Device: 4, 5, 6
Function: 0
Offset: B8h
Access as a Dword
Bit Type
Reset
Value
Description
14 RW 0 DISABLE_8B_CRITICAL_WORD. Disable critical word first optimization
13 RW 0 DDR_CLK_TRISTATE_DISABLE. When 0, DDR clock drivers will always be
enabled.
12 RW 0 CS_ODT_TRISTATE_DISABLE. When set low(0) CS and ODT drivers will
always be enabled.
11 RW 0 FLOAT_EN. When set, the address and command lines will float to save power
when commands are not being sent out.
10:6 RW 7 PRECASRDTHRESHOLD. Threshold above which Medium-Low Priority reads
can PRE-CAS write requests.
5RW0DISABLE_ISOC_RBC_RESERVE. When set this bit will prevent any RBC's
from being reserved for ISOC.
3RW0ENABLE2N. Enable 2n Timing.
2:0 RW 0 PRIORITYCOUNTER. Upper 3 MSB of 8 bit priority time out counter.