Datasheet

Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 2 47
Register Description
2.10.3 MC_SSRSTATUS
Provides the status of the operation specified in MC_SSRCONTROL.SSR_Mode.
2.11 Integrated Memory Controller Channel Control
Registers
2.11.1 MC_CHANNEL_0_REFRESH_THROTTLE_SUPPORT
MC_CHANNEL_1_REFRESH_THROTTLE_SUPPORT
MC_CHANNEL_2_REFRESH_THROTTLE_SUPPORT
This register supports Self Refresh and Thermal Throttle functions.
Device: 3
Function: 2
Offset: 4Ch
Access as a Dword
Bit Type
Reset
Value
Description
29:27 RW 0 SKIP_SCRUB. This bit disables patrol scrubs to the channel corresponding to
the bit that is set. Bit 27 disables patrol scrubs to channel 0, bit 28 disables
patrol scrubs to channel 1 and bit 29 disables patrol scrubs to channel 2. This
bit can only be set or reset on a system with patrol scrub enabled, and only
after transitioning the SSR_CONTROL.SSR_MODE to idle and polling until
SSRSTATUS.CMPLT is 1. When mirroring is enabled this field must not be set.
26 RW 0 SCRUBISSUED. When Set, the scrub address registers contain the last scrub
address issued.
25 - - RSVD.
24 RW 0 STARTSCRUB. When Set, the Patrol scrub engine will start from the address in
the scrub address registers. Once the scrub is issued this bit is reset.
23:0 RW 0 SCRUBINTERVAL. Defines the interval in DCLKS between patrol scrub
requests. The calculation for this register to get a scrub to every line in 24
hours is:
((36400)/(memory capacity/64))/cycle time of DCLK
For 512MB at DDR3-800:
(36400/((2^29)/64))/1.25 x 10^-9 = 3471374 = 0x34F80E
Device: 3
Function: 2
Offset: 60h
Access as a Dword
Bit Type
Reset
Value
Description
1RO0INPROGRESS. Patrol Scrub operation in progress. This bit is set by hardware
once scrubbing operation has started. It is cleared once operation is complete
or fails.
0RO0CMPLT. Patrol Scrub operation complete. Set by hardware once operation is
complete. Bit is cleared by hardware when a new operation is enabled.