Datasheet

Register Description
46 Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 2
2.9.5 MC_SCRUBADDR_HI
This register pair contains part of the address of the last patrol scrub request issued.
When running memtest, the failing address is logged in this register on memtest
errors. Software can write the next address into this register. Scrubbing must be
disabled to reliably read and write this register.
2.10 Integrated Memory Controller RAS Registers
2.10.1 MC_SSRCONTROL
scrubbing control. This register allows the enabling of sparing, patrol scrubbing and
demand scrubbing.
2.10.2 MC_SCRUB_CONTROL
Contains the Scrub control parameters and status.
Device: 3
Function: 0
Offset: 7Ch
Access as a Dword
Bit Type
Reset
Value
Description
12 RO 0 MEMBIST_INPROGRESS. When this bit is asserted by hardware
MemTest/MemInit is in progress.
11 RO 0 MEMBIST_CMPLT. When this bit is asserted by hardware MemTest/MemInit is
complete.
10 WO 0 RESET_MEMBIST_STATUS. When this bit is written to a 1, the status field
MEMBIST_CMPLT is cleared.
9:8 RW 0 CHNL. Can be written to specify the next scrub address with STARTSCRUB in
the MC_SCRUB_CONTROL register. Contains the channel address of the last
patrol scrub issued.
7:6 RW 0 DIMM. Contains the dimm of the last scrub issued. Can be written to specify
the next scrub address with STARTSCRUB in the MC_SCRUB_CONTROL register.
5:4 RW 0 RANK. Contains the rank of the last scrub issued. Can be written to specify the
next scrub address with STARTSCRUB in the MC_SCRUB_CONTROL register.
3:0 RW 0 BANK. Contains the bank of the last scrub issued. Can be written to specify the
next scrub address with STARTSCRUB in the MC_SCRUB_CONTROL register.
Device: 3
Function: 2
Offset: 48h
Access as a Dword
Bit Type
Reset
Value
Description
14:7 RW 0 SCRATCHPAD. This field is available as a scratchpad for Scrubbing operations.
6RW0DEMAND_SCRUB_EN. Enable Demand Scrubs.
1:0 RW 0 SSR_MODE. Spare control enable.
00: Idle
01: Scrub
10: Spare