Datasheet

Register Description
44 Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 2
2.9.3 MC_MAX_DOD
Defines the MAX number of DIMMS, RANKS, BANKS, ROWS, COLS among all DIMMS
populating the three channels. The Memory Init logic uses this register to cycle through
all the memory addresses writing all 0's to initialize all locations. This register is also
used for scrubbing and must always be programmed if any DODs are programmed.
Device: 3
Function: 0
Offset: 54h
Access as a Dword
Bit Type
Reset
Value
Description
16 RW 0 INTERRUPT_SELECT_NMI. NMI enable. Set to enable NMI signaling. Clear to
disable NMI signaling. If both NMI and SMI enable bits are set, then only SMI is
sent.
15 RW 0 INTERRUPT_SELECT_SMI. SMI enable. Set to enable SMI signaling. Clear to
disable SMI signaling. If both NMI and SMI enable bits are set, then only SMI is
sent. This bit functions the same way in Mirror and Independent Modes.
The possible SMI events enabled by this bit are:
Any one of the error counters MC_COR_ECC_CNT_X meets the value of
SMI_ERROR_THRESHOLD field of this register.
MC_RAS_STATUS.REDUNDANCY_LOSS bit is set to 1.
14:0 RW 0 SMI_ERROR_THRESHOLD. Defines the error threshold to compare against
the per-DIMM error counters MC_COR_ECC_CNT_X, which are also 15 bits.
Device: 3
Function: 0
Offset: 64h
Access as a Dword
Bit Type
Reset
Value
Description
10:9 RW 0 MAXNUMCOL. Maximum Number of Columns.
00: 2^10 columns
01: 2^11 columns
10: 2^12 columns
11: RSVD.
8:6 RW 0 MAXNUMROW. Maximum Number of Rows.
000: 2^12 Rows
001: 2^13 Rows
010: 2^14 Rows
011: 2^15 Rows
100: 2^16 Rows
Others: RSVD.
5:4 RW 0 MAXNUMBANK. Max Number of Banks.
00: Four-banked
01: Eight-banked
10: Sixteen-banked.
3:2 RW 0 MAXNUMRANK. Maximum Number of Ranks.
00: Single Ranked
01: Double Ranked
10: Quad Ranked.