Intel® Xeon® Processor 5600 Series Datasheet, Volume 2 March 2010 Reference Number: 323370-001
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Contents 1 Introduction .............................................................................................................. 7 1.1 References ......................................................................................................... 7 2 Register Description .................................................................................................. 9 2.1 Register Terminology ........................................................................................... 9 2.
2.11.6 2.12 MC_CHANNEL_0_SCHEDULER_PARAMS MC_CHANNEL_1_SCHEDULER_PARAMS MC_CHANNEL_2_SCHEDULER_PARAMS....................................................52 2.11.7 MC_CHANNEL_0_PAGETABLE_PARAMS2 MC_CHANNEL_1_PAGETABLE_PARAMS2 MC_CHANNEL_2_PAGETABLE_PARAMS2...................................................52 Memory Thermal Control ....................................................................................53 2.12.1 MC_THERMAL_STATUS0 MC_THERMAL_STATUS1 MC_THERMAL_STATUS2............................
Figures Tables 1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 3-1 3-2 3-3 3-4 3-5 3-6 3-7 References ......................................................................................................... 7 Functions Specifically Handled by the Processor..................................................... 12 Device 0, Function 0: Generic Non-core Registers ..................................................
Revision History Revision -001 Description Initial release.
Introduction 1 Introduction The Intel® Xeon® processor 5600 series is the next generation DP server/workstation processor based on the Intel® Xeon® Processor 5500 Series architecture, and utilizing 32 nm process technology. The Intel Xeon processor 5600 series upgrades Intel® 5500 platforms, and provides the following new features and capabilities: • Up to 6-core operation (up to 12 threads per socket with Intel® Hyper-Threading Technology) • 12 MB of shared Last-Level Cache • Support for DDR3L (1.
Introduction 8 Intel® Xeon® Processor 5600 Series Datasheet Volume 2
Register Description 2 Register Description The processor supports PCI configuration space accesses using the mechanism denoted as Configuration Mechanism in the PCI specification as defined in the PCI Local Bus Specification, as well as the PCI Express enhanced configuration mechanism as specified in the PCI Express Base Specification. All the registers are organized by bus, device, function, etc. as defined in the PCI Express Base Specification.
Register Description Term 2.2 Description Reserved Bits Some of the processor registers described in this section contain reserved bits. These bits are labeled “Reserved”. Software must deal correctly with fields that are reserved. On reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. On writes, software must ensure that the values of reserved bit positions are preserved.
Register Description DID of 2DA0h. Device 4, Function 1 contains the address registers for Integrated Memory Controller Channel 0 and resides at DID of 2DA1h. Device 4, Function 2 contains the rank registers for Integrated Memory Controller Channel 0 and resides at DID of 2DA2h. Device 4, Function 3 contains the thermal control registers for Integrated Memory Controller Channel 0 and resides at DID of 2DA3h. • Device 5: Integrated Memory Controller Channel 1.
Register Description Table 2-1.
Register Description 2.4 Detailed Configuration Space Maps Table 2-2.
Register Description Table 2-3.
Register Description Table 2-4.
Register Description Table 2-5.
Register Description Table 2-6.
Register Description Table 2-7.
Register Description Table 2-8.
Register Description Table 2-9.
Register Description Table 2-10.
Register Description Table 2-11.
Register Description Table 2-12.
Register Description Table 2-13.
Register Description Table 2-14.
Register Description Table 2-15.
Register Description Table 2-16.
Register Description Table 2-17.
Register Description Table 2-18.
Register Description Table 2-19.
Register Description Table 2-20.
Register Description Table 2-21.
Register Description Table 2-22.
Register Description Table 2-23.
Register Description Table 2-24.
Register Description Table 2-25. Device 6, Function 3: Integrated Memory Controller Channel 2 Thermal Control Registers DID VID 00h MC_COOLING_COEF2 80h PCISTS PCICMD 04h MC_CLOSED_LOOP2 84h 08h MC_THROTTLE_OFFSET2 CCR RID HDR SID 2.
Register Description 2.5.1 DID - Device Identification Register This 16-bit register combined with the Vendor Identification register uniquely identifies the Function within the processor. Writes to this register have no effect. See Table 2-1 for the DID of each processor function. 2.5.
Register Description defined and is implementation dependent. This does not result in all of the power savings of a reduced number of core product, but does save more power than even the deepest sleep state. . 2.6.2 Device: Function: Offset: Access as 0 0 80h a Dword Bit Type Reset Value 16 RW1S 0 LOCK. Once written to 1, changes to this register cannot be made. 8 RWL 0 MT_DISABLE. Disables multi-threading (2 logical threads per core) in all cores if set to 1. 2:0 RWL 0 CORE_COUNT.
Register Description 2.7 SAD - System Address Decoder Registers 2.7.1 SAD_MCSEG_BASE Global register for MCSEG address space. These are designed to look just like the cores SMRR type registers. Device: Function: Offset: Access as Bit 0 1 60h a Qword Type Reset Value 63:40 39:19 RSVD. RW 0 18:0 2.7.2 Description BASE_ADDRESS. Specifies the base address of the MCSEG. Must be aligned on 512KB or greater boundary. RSVD. SAD_MCSEG_MASK Global register for MCSEG address space.
Register Description Device: Function: Offset: Access as Bit 0 1 70h a Qword Type Reset Value 63:40 39:19 RSVD. RW 0 BASE_ADDRESS. Specifies the base address of the MESEG. Must be aligned on 512KB or greater boundary. 18:0 2.7.4 Description RSVD. SAD_MESEG_MASK Register for ME stolen range address space. They are designed to look just like the core SMRR type registers. Device: Function: Offset: Access as 0 1 78h a Qword Type Reset Value 39:19 RW 0 MASK. Mask of MESEG.
Register Description 2.8.2 Device: Function: Offset: Access as 2 0, 4 58h a Dword 9:8 RW 1 NCB. NCB Channel VN0 Credits. 7:6 RW 1 DRS. DRS Channel VN0 Credits. 5:4 RW 1 NDR. NDRChannel VN0 Credits. 3:2 RW 1 SNP. SNP Channel VN0 Credits. 1:0 RW 1 HOM. HOMChannel VN0 Credits. QPI_RMT_QPILP1_STAT_L0 QPI_RMT_QPILP1_STAT_L1 Remote’s Intel QPI Parameter 1 Value register. 2.8.3 Device: Function: Offset: Access as 2 0, 4 C4h a Dword Bit Type Reset Value Description 11 - BP_Request.
Register Description 2.8.4 Device: Function: Offset: Access as 2 2,3 6Ch a Dword Bit Type Reset Value 31 RW 0 RETRAIN_NOW. This bit generates a retraining event with the provided retraining parameters when enabled only during at-speed operation 27 RW 0 LA_LOAD_DISABLE. Disables the loading of the effective values of the Intel® QuickPath CSRs when set. 23 RW 0 ENABLE_PRBS. Enables LFSR pattern during bitlock/training. 22 RW 0 ENABLE_SCRAMBLE. Enables data scrambling through LFSR.
Register Description 2.9.1 MC_SMI_DIMM_ERROR_STATUS SMI DIMM error threshold overflow status register. This bit is set when the per-DIMM error counter exceeds the specified threshold. The bit is reset by BIOS. Device: Function: Offset: Access as 3 0 50h a Dword Bit Type Reset Value 13:12 RW0C 0 REDUNDANCY_LOSS_FAILING_DIMM. The ID for the failing DIMM when redundancy is lost. 11:0 RW0C 0 DIMM_ERROR_OVERFLOW_STATUS. This 12-bit field is the per dimm error overflow status bits.
Register Description Device: Function: Offset: Access as 2.9.3 3 0 54h a Dword Bit Type Reset Value 16 RW 0 INTERRUPT_SELECT_NMI. NMI enable. Set to enable NMI signaling. Clear to disable NMI signaling. If both NMI and SMI enable bits are set, then only SMI is sent. 15 RW 0 INTERRUPT_SELECT_SMI. SMI enable. Set to enable SMI signaling. Clear to disable SMI signaling. If both NMI and SMI enable bits are set, then only SMI is sent. This bit functions the same way in Mirror and Independent Modes.
Register Description 2.9.4 Device: Function: Offset: Access as 3 0 64h a Dword Bit Type Reset Value 1:0 RW 0 Description MAXNUMDIMMS. Maximum Number of Dimms. 00: 1 Dimm 01: 2 Dimms 10: 3 Dimms 11: RSVD. MC_RD_CRDT_INIT These registers contain the initial read credits available for issuing memory reads. TAD read credit counters are loaded with the corresponding values at reset and anytime this register is written.
Register Description 2.9.5 MC_SCRUBADDR_HI This register pair contains part of the address of the last patrol scrub request issued. When running memtest, the failing address is logged in this register on memtest errors. Software can write the next address into this register. Scrubbing must be disabled to reliably read and write this register. Device: Function: Offset: Access as 3 0 7Ch a Dword Bit Type Reset Value 12 RO 0 MEMBIST_INPROGRESS.
Register Description Device: Function: Offset: Access as 3 2 4Ch a Dword Bit Type Reset Value 29:27 RW 0 SKIP_SCRUB. This bit disables patrol scrubs to the channel corresponding to the bit that is set. Bit 27 disables patrol scrubs to channel 0, bit 28 disables patrol scrubs to channel 1 and bit 29 disables patrol scrubs to channel 2. This bit can only be set or reset on a system with patrol scrub enabled, and only after transitioning the SSR_CONTROL.SSR_MODE to idle and polling until SSRSTATUS.
Register Description 2.11.2 Device: Function: Offset: Access as 4, 5, 6 0 68h a Dword Bit Type Reset Value 5 RW 0 RSVD. Description 4 RW 0 RSVD. 3:2 RW 0 INC_ENTERPWRDWN_RATE. Powerdown rate will be increased during thermal throttling based on the following configurations. 00: tRANKIDLE (Default) 01: 16 10: 24 11: 32 1 RW 0 DIS_OP_REFRESH. When set, the refresh engine will not issue opportunistic refresh. 0 RW 0 ASR_PRESENT.
Register Description Device: Function: Offset: Access as 4, 5, 6 0 80h a Dword 22:19 RW 0 tsrWrTRd. Minimum delay between a write followed by a read to the same rank. 0000: 10 0001: 11 0010: 12 0011: 13 0100: 14 0101: 15 0110: 16 0111: 17 1000: 18 1001: 19 1010: 20 1011: 21 1100: 22 1101: 23 1110: 24 1111: 25 18:15 RW 0 tddRdTWr. Minimum delay between Read followed by a Write to different DIMMs.
Register Description Device: Function: Offset: Access as 2.11.3 4, 5, 6 0 80h a Dword 10:7 RW 0 tsrRdTWr. Minimum delay between Read followed by a write to the same rank. 0000: RSVD 0001: RSVD 0010: RSVD 0011: 5 0100: 6 0101: 7 0110: 8 0111: 9 1000: 10 1001: 11 1010: 12 1011: 13 1100: 14 1101: RSVD 1110: RSVD 1111: RSVD 6:4 RW 0 tddRdTRd. Minimum delay between reads to different DIMMs. 000: 2 001: 3 010: 4 011: 5 100: 6 101: 7 110: 8 111: 9 3:1 RW 0 tdrRdTRd.
Register Description Device: Function: Offset: Access as Bit Type Reset Value RW 0 tTHROT_OPPREF. The minimum time between two opportunistic refreshes. Should be set to tRFC in DCLKs. Zero is an invalid encoding. A value of 1 should be programmed to disable the throttling of opportunistic refreshes.
Register Description Device: Function: Offset: Access as 2.11.6 4, 5, 6 0 78h a Dword Bit Type Reset Value 14:5 RW 0 tRANKIDLE: Rank will go into powerdown after it has been idle for the specified number of DCLKs. tRANKIDLE covers max(txxxPDEN). Minimum value is tWRAPDEN. If CKE is being shared between ranks then both ranks must be idle for this amount of time. A Power Down Entry command will be requested for a rank after this number of DCLKs if no request to the rank is in the MC.
Register Description Device: Function: Offset: Access as 4, 5, 6 0 DCh a Dword Bit Type Reset Value Description 27 RW 0 ENABLEADAPTIVEPAGECLOSE. When set, enables Adaptive Page Closing. 26:18 RW 0 MINPAGECLOSELIMIT. Upper 9 MSBs of a 13-bit threshold limit. When the mistake counter falls below this threshold, a less aggressive page close interval (larger) is selected. 17:9 RW 0 MAXPAGECLOSELIMIT. Upper 9 bits of a 13-bit threshold limit.
Register Description Device: Function: Offset: Access as 2.12.3 4, 5, 6 3 9Ch a Dword 2 RW 0 REF_2X. Force 2x refresh as long as DDR_THERM# is asserted (low). 1 RW 0 DISABLE_EXTTS. Response to DDR_THERM# pin is disabled. ASSERTION and DEASSERTION fields in the register MC_DDR_THERM0_STATUS are frozen. 0 RW1S 0 LOCK. When set, all bits in this register are RO and cannot be written. Reset will clear the lock.
Register Description 2.12.5 MC_DDR_THERM1_STATUS0 MC_DDR_THERM1_STATUS1 MC_DDR_THERM1_STATUS2 This register contains the status portion of the DDR_THERM2# pin functionality (that is, what is happening or has happened with respect to the pin). Device: Function: Offset: Access as Bit 4, 5, 6 3 A8h a Dword Type Reset Value Description 2 RO 0 ASSERTION. An assertion edge was seen on DDR_THERM#. Write-1-to-clear. 1 RO 0 DEASSERTION. A de-assertion edge was seen on DDR_THERM#. Write-1-toclear.
Register Description 56 Intel® Xeon® Processor 5600 Series Datasheet Volume 2
Functional Description 3 Functional Description This chapter describes the functional differences between the Intel Xeon processor 5500 series and Intel Xeon processor 5600 series. For more information on the Intel Xeon processor 5500 series features and functionality, refer to the Intel® Xeon® Processor 5500 Series Datasheet, Volume 2. 3.1 Integrated Memory Controller The Intel Xeon processor 5600 series integrated memory controller supports DDR3 800, DDR3 1066 and DDR3 1333 memory technologies.
Functional Description Table 3-1. Integrated Memory Controller Feature Comparison (Sheet 2 of 2) Feature Intel® Xeon® Processor 5500 Series Intel® Xeon® Processor 5600 Series No Yes. Channel 2 can be used as a spare for channels on the same socket. All channels must be identically populated. Not supported when in Lockstep Mode RAS - Sparing Channel Support RAS - Mirroring Channel Support Yes. Between Ch 0 and Ch 1 of the same socket. Ch2 may not be populated. Not with lockstep.
Functional Description 3.2.2 RDIMM 1.35 V Configurations Table 3-3. RDIMM (1.35 V) Support DIMM Slots per Channel DIMMS Populated per Channel 2 1 Reg. DDR3L 1.35 V ECC 800, 1066, 1333 SR or DR 2 1 Reg. DDR3L 1.35 V ECC 800 QR only 2 2 Reg. DDR3L 1.35 V ECC 800, 1066 Mixing SR, DR 2 2 Reg. DDR3L 1.35 V ECC 800 Mixing SR, DR, QR 3 1 Reg. DDR3L 1.35 V ECC 800, 1066, 1333 SR or DR 3 1 Reg. DDR3L 1.35 V ECC 800 QR only 3 2 Reg. DDR3L 1.
Functional Description 1. 2. 3. 4. 5. 60 The Intel Xeon processor 5600 series supports all Intel Xeon processor 5500 series POR memory configurations. Any combination of x8 and x16 UDIMMs, with 1Gb or 2Gb DRAM density, is supported. Populate DIMMs starting with slot 0, furthest from the CPU. Any combination of x8 UDIMMs, with 1Gb or 2Gb DRAM density, is supported. 2 DIMMs Populated per Channel at 1333 MT/s is only supported on UDIMMs with ECC support.
Functional Description 3.3.2 UDIMM 1.35V Configurations Table 3-5. UDIMM (1.35V) Support Platforms with UDIMM Only Routing DIMM Slots per Channel DIMMs Populated per Channel DIMM Type 2 1 Unbuffered DDR3L 1.35V (w/ ECC) 800, 1066, 1333 SR or DR 2 2 Unbuffered DDR3L 1.
Functional Description 3.5 Memory Error Signaling 3.5.1 Enabling SMI/NMI for Memory Corrected Errors The MC_SMI_CNTRL register has enables for SMI and NMI interrupts. Only one should be set. Whichever type of interrupt is enabled will be triggered if: • a DIMM error counter exceeds the threshold • redundancy is lost on a mirrored configuration or 3.5.2 Identifying the Cause of an Interrupt Table 3-6 defines how to determine the cause of an interrupt. Table 3-6.
Functional Description 3.7 2X Refresh The Intel Xeon processor 5600 series supports 2X refresh via two mechanisms. The traditional software-based mechanism (via MC_CLOSED_LOOP register) supported on Intel Xeon processor 5500 series, and a new hardware-based mechanism (via DDR_THERM2# pin). 1. SW Based - when MC_CLOSED_LOOP.REF_2X_NOW configuration bit is set. 2. HW Based - when DDR_THERM2# pin is asserted and its corresponding MC_DDR_THERM1_COMMANDX.REF_2X register bit is set.
Functional Description 64 Intel® Xeon® Processor 5600 Series Datasheet Volume 2
