Intel Core Duo Processor and Intel Core Solo Processor on 65 nm Process

Datasheet 73
Package Mechanical Specifications and Pin Information
C20 DBR# CMOS Output
C21 BSEL[2] CMOS Output
C22 VSS Power/Other
C23 RSVD Reserved
C24 RSVD Reserved
C25 VSS Power/Other
C26 TEST1 Test
D1 VSS Power/Other
D2 RSVD Reserved
D3 RSVD Reserved
D4 VSS Power/Other
D5 STPCLK# CMOS Input
D6 PWRGOOD CMOS Input
D7 SLP# CMOS Input
D8 VSS Power/Other
D9 VCC Power/Other
D10 VCC Power/Other
D11 VSS Power/Other
D12 VCC Power/Other
D13 VSS Power/Other
D14 VCC Power/Other
D15 VCC Power/Other
D16 VSS Power/Other
D17 VCC Power/Other
D18 VCC Power/Other
D19 VSS Power/Other
D20 IERR# Open Drain Output
D21
PROCHOT
#
Open Drain
Input/
Output
D22 RSVD Reserved
D23 VSS Power/Other
Table 19. Pin Listing by Pin Number
Pin
Number
Pin Name
Signal
Buffer Type
Direction
D24 DPWR#
Common
Clock
Input
D25 TEST2 Test
D26 VSS Power/Other
E1 DBSY#
Common
Clock
Input/
Output
E2 BNR#
Common
Clock
Input/
Output
E3 VSS Power/Other
E4 HITM#
Common
Clock
Input/
Output
E5 DPRSTP# CMOS Input
E6 VSS Power/Other
E7 VCC Power/Other
E8 VSS Power/Other
E9 VCC Power/Other
E10 VCC Power/Other
E11 VSS Power/Other
E12 VCC Power/Other
E13 VCC Power/Other
E14 VSS Power/Other
E15 VCC Power/Other
E16 VSS Power/Other
E17 VCC Power/Other
E18 VCC Power/Other
E19 VSS Power/Other
E20 VCC Power/Other
E21 VSS Power/Other
E22 D[0]#
Source
Synch
Input/
Output
E23 D[7]#
Source
Synch
Input/
Output
E24 VSS Power/Other
Table 19. Pin Listing by Pin Number
Pin
Number
Pin Name
Signal
Buffer Type
Direction