Datasheet

Contents
3
Contents
1.0 Introduction..................................................................................................................7
1.1 Terminology...........................................................................................................8
1.1.1 Processor Packaging Terminology...........................................................8
1.2 References ............................................................................................................9
2.0 Electrical Specifications........................................................................................11
2.1 System Bus and GTLREF...................................................................................11
2.2 Power and Ground Pins ......................................................................................11
2.3 Decoupling Guidelines ........................................................................................11
2.3.1 VCC
Decoupling.....................................................................................12
2.3.2 System Bus AGTL+ Decoupling.............................................................12
2.3.3 System Bus Clock (BCLK[1:0]) and Processor Clocking .......................12
2.4 Voltage Identification...........................................................................................12
2.4.1 Phase Lock Loop (PLL) Power and Filter...............................................13
2.5 Reserved, Unused Pins, and TESTHI[10:0]........................................................15
2.6 System Bus Signal Groups .................................................................................16
2.7 Asynchronous GTL+ Signals...............................................................................17
2.8 Test Access Port (TAP) Connection....................................................................17
2.9 Maximum Ratings................................................................................................18
2.10 Processor DC Specifications...............................................................................18
2.11 AGTL+ System Bus Specifications .....................................................................21
2.12 System Bus AC Specifications............................................................................22
2.13 Processor AC Timing Waveforms .......................................................................25
3.0 System Bus Signal Quality Specifications....................................................31
3.1 BCLK Signal Quality Specifications and Measurement Guidelines.....................31
3.2 System Bus Signal Quality Specifications and Measurement Guidelines...........32
3.3 System Bus Signal Quality Specifications and Measurement Guidelines...........33
3.3.1 Overshoot/Undershoot Guidelines .........................................................33
3.3.2 Overshoot/Undershoot Magnitude .........................................................34
3.3.3 Overshoot/Undershoot Pulse Duration...................................................34
3.3.4 Activity Factor.........................................................................................34
3.3.5 Reading Overshoot/Undershoot Specification Tables............................35
3.3.6 Determining if a System Meets the Over/Undershoot Specifications.....35
4.0 Package Mechanical Specifications.........................................................................43
4.1 Package Load Specifications ..............................................................................46
4.2 Processor Insertion Specifications ......................................................................47
4.3 Processor Mass Specifications ...........................................................................47
4.4 Processor Materials.............................................................................................47
4.5 Processor Markings.............................................................................................48
4.6 Processor Pin-Out Coordinates...........................................................................48
5.0 Pin Listing and Signal Definitions...........................................................................51
5.1 Processor Pin Assignments ................................................................................51
5.1.1 Pin Listing by Pin Name .........................................................................51
5.1.2 Pin Listing by Pin Number......................................................................57