Datasheet

Intel
®
Pentium
®
4 Processor in the 423-pin Package
20
2. These voltages are targets only. A variable voltage source should exist on systems in the event that a
different voltage is required. See Section 2.4 and Table 2 for more information.
3. The voltage specification requirements are measured across V
CC_SENSE
and V
SS_SENSE
pins at the socket with
a 100MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The
maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the
system is not coupled in the scope probe.
4. The processor should not be subjected to any static V
CC
and I
CC
combination wherein V
CC
exceeds V
CC_MID
+
0.055*(1 - I
CC
/I
CC_MAX
) [V]. Moreover, V
cc
should never exceed V
CC_MAX
(VID). Failure to adhere to this
specification can shorten the processor lifetime.
5. Maximum current is defined at V
CC_MID
.
6. The current specified is also for AutoHALT State.
7. The maximum instantaneous current the processor will draw while the thermal control circuit is active as
indicated by the assertion of PROCHOT# is the same as the maximum I
CC
for the processor.
8. I
CC
Stop-Grant, I
CC
Sleep, and I
CC
Deep Sleep are specified at V
CC_MAX.
9. These specifications apply to “1.7V” processors, i.e., those with a VID = ‘00110’.
10.These specifications apply to “1.75V” processors, i.e., those with a VID = ‘00100’.
NOTES:.
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to the falling edge of
BCLK1.
3. The V
L
and V
H
used to calculate V
CROSS
are the actual V
L
and V
H
seen by the processor.
4. Overshoot is defined as the absolute value of the maximum voltage allowed above the V
H
level.
5. Undershoot is defined as the absolute value of the maximum voltage allowed below the V
SS
level.
6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback
and the maximum Falling Edge Ringback.
7. Threshold Region is defined as a region centered about the crossing voltage in which the differential receiver
switches. It includes input threshold hysteresis.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V
IL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
Table 6. System Bus Differential BCLK Specifications
Symbol Parameter Min Typ Max Unit Figure Notes
1
V
L
Input Low Voltage 0 V 5
V
H
Input High Voltage 0.660 0.710 0.850 V 5
V
CROSS
Crossing Voltage 0.45*(V
H
-V
L
)0.5*(V
H
-V
L
) 0.55*(V
H
-V
L
)V 5 2, 3
V
OV
Overshoot N/A N/A 0.3 V 5 4
V
US
Undershoot N/A N/A 0.3 V 5 5
V
RBM
Ringback Margin 0.200 V 5 6
V
TH
Threshold Region V
CROSS
-0.100 V
CROSS
+0.100 V 5 7
Table 7. AGTL+ Signal Group DC Specifications
Symbol Parameter Min Max Unit Notes
1
VIL Input Low Voltage -0.150 GTLREF - 100mV V 2, 6
V
IH Input High Voltage GTLREF + 100mV V
CC
V3, 4, 6
V
OH Output High Voltage GTLREF + 100mV V
CC
V4, 6
I
OL Output Low Current
V
CC
/ (0.5*Rtt_min +
R
ON_MIN)
mA 6
I
LI Input Leakage Current ± 100 µA
I
LO Output Leakage Current ± 100 µA
R
ON Buffer On Resistance 5 11 Ω 5