Desktop 4th Generation Specification Sheet
Table Of Contents
- Contents
- Revision History
- 1.0 Introduction
- 2.0 Interfaces
- 3.0 Technologies
- 3.1 Intel® Virtualization Technology (Intel® VT)
- 3.2 Intel® Trusted Execution Technology (Intel® TXT)
- 3.3 Intel® Hyper-Threading Technology (Intel® HT Technology)
- 3.4 Intel® Turbo Boost Technology 2.0
- 3.5 Intel® Advanced Vector Extensions 2.0 (Intel® AVX2)
- 3.6 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)
- 3.7 Intel® Transactional Synchronization Extensions - New Instructions (Intel® TSX-NI)
- 3.8 Intel® 64 Architecture x2APIC
- 3.9 Power Aware Interrupt Routing (PAIR)
- 3.10 Execute Disable Bit
- 3.11 Supervisor Mode Execution Protection (SMEP)
- 4.0 Power Management
- 4.1 Advanced Configuration and Power Interface (ACPI) States Supported
- 4.2 Processor Core Power Management
- 4.3 Integrated Memory Controller (IMC) Power Management
- 4.4 PCI Express* Power Management
- 4.5 Direct Media Interface (DMI) Power Management
- 4.6 Graphics Power Management
- 5.0 Thermal Management
- 5.1 Desktop Processor Thermal Profiles
- 5.2 Thermal Metrology
- 5.3 Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 1.1
- 5.4 Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 2.0
- 5.5 Processor Temperature
- 5.6 Adaptive Thermal Monitor
- 5.7 THERMTRIP# Signal
- 5.8 Digital Thermal Sensor
- 5.9 Intel® Turbo Boost Technology Thermal Considerations
- 6.0 Signal Description
- 6.1 System Memory Interface Signals
- 6.2 Memory Reference and Compensation Signals
- 6.3 Reset and Miscellaneous Signals
- 6.4 PCI Express*-Based Interface Signals
- 6.5 Display Interface Signals
- 6.6 Direct Media Interface (DMI)
- 6.7 Phase Locked Loop (PLL) Signals
- 6.8 Testability Signals
- 6.9 Error and Thermal Protection Signals
- 6.10 Power Sequencing Signals
- 6.11 Processor Power Signals
- 6.12 Sense Signals
- 6.13 Ground and Non-Critical to Function (NCTF) Signals
- 6.14 Processor Internal Pull-Up / Pull-Down Terminations
- 7.0 Electrical Specifications
- 8.0 Package Mechanical Specifications
- 9.0 Processor Ball and Signal Information
Symbol Definition and Conditions Min Max Units Notes
1
V
n
Negative-Edge Threshold
Voltage
0.275 *
V
CCIO_TERM
0.500
* V
CCIO_TERM
V —
V
p
Positive-Edge Threshold
Voltage
0.550 *
V
CCIO_TERM
0.725 *
V
CCIO_TERM
V —
C
bus
Bus Capacitance per Node N/A 10 pF —
C
pad
Pad Capacitance 0.7 1.8 pF —
Ileak000 leakage current at 0 V — 0.6 mA —
Ileak025
leakage current at 0.25*
V
CCIO_TERM
— 0.4 mA —
Ileak050
leakage current at 0.50*
V
CCIO_TERM
— 0.2 mA —
Ileak075
leakage current at 0.75*
V
CCIO_TERM
— 0.13 mA —
Ileak100
leakage current at
V
CCIO_TERM
— 0.10 mA —
Notes: 1. V
CCIO_TERM
supplies the PECI interface. PECI behavior does not affect V
CCIO_TERM
minimum /
maximum specifications.
2. The leakage specification applies to powered devices on the PECI bus.
3. The PECI buffer internal pull-up resistance measured at 0.75* V
CCIO_TERM
.
Input Device Hysteresis
The input buffers in both client and host models must use a Schmitt-triggered input
design for improved noise immunity. Use the following figure as a guide for input
buffer design.
Figure 23. Input Device Hysteresis
Minimum V
P
Maximum V
P
Minimum V
N
Maximum V
N
PECI High Range
PECI Low Range
Valid Input
Signal Range
Minimum
Hysteresis
V
TTD
PECI Ground
7.8.2
Processor—Electrical Specifications
Desktop 4th Generation Intel
®
Core
™
Processor Family, Desktop Intel
®
Pentium
®
Processor Family, and Desktop Intel
®
Celeron
®
Processor Family
Datasheet – Volume 1 of 2 December 2013
104 Order No.: 328897-004