Intel® 82575 Gigabit Ethernet Controller Design Guide V1.
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82575 Ethernet Controller Design Guide Contents 1.0 Introduction .............................................................................................................. 1 1.1 Scope ................................................................................................................ 1 1.2 Reference Documents .......................................................................................... 2 2.0 PCI Express Port Connection to the Device ..........................................
82575 Ethernet Controller Design Guide 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 Frequency Tolerance ..........................................................................................32 Temperature Stability and Environmental Requirements..........................................32 Calibration Mode................................................................................................33 Load Capacitance............................................................................................
82575 Ethernet Controller Design Guide Revision History Date Revision Description 0.25 Jan 2006 Initial publication of preliminary design guide information. 0.50 July 2006 Added features listings, NC-SI, LED, strapping, pull-up/pull-down information. 0.75 March 2007 Changed classification to “Confidential”; updated crystal layout guidance; removed thermal sensor references; removed password requirements for schematic, checklist, and symbol files; updated EEPROM selection information. 1.
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82575 Ethernet Controller Design Guide 1.0 Introduction The Intel® 82575 Ethernet Controller is a single, compact component that offers two fully-integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) ports. This device uses the PCI Express* (PCIe) architecture (Rev. 1.1RD). The 82575 enables two-port implementation in a relatively small area and can be used for server and workstation network designs with critical space constraints. The 82575 provides: • a standard IEEE 802.
2575 Ethernet Controller Design Guide 1.2 Reference Documents This application assumes that the designer is acquainted with high-speed design and board layout techniques. The following documents provide additional information: • 82575 Ethernet Controller Product Datasheet. Intel Corporation. • PCI Express Base Specification, Revision 1.1. PCI Special Interest Group. • PCI Express Card Electromechanical Specification, Revision 1.0a. PCI Special Interest Group.
82575 Ethernet Controller Design Guide 2.0 PCI Express Port Connection to the Device PCI Express (PCIe*) is a dual simplex point-to-point serial differential low-voltage interconnect. The signaling bit rate is 2.5 Gbps per lane per direction. Each port consists of a group of transmitters and receivers located on the same chip. Each lane consists of a transmitter and a receiver pair. A link between the ports of two devices is a collection of lanes.
82575 Ethernet Controller Design Guide • If Maximum Link Width = x2, then the 82575 Ethernet Controller negotiates to either x2 or x1 • If Maximum Link Width = x1, then the 82575 Ethernet Controller only negotiates to x1 2.3.2 Polarity Inversion If polarity inversion is detected the Receiver must invert the received data. During the training sequence, the Receiver looks at Symbols 6-15 of TS1 and TS2 as the indicator of lane polarity inversion (D+ and D- are swapped).
82575 Ethernet Controller Design Guide Lane Reversal in x4 mode x4 3 Reversal 2 1 0 2 1 0 x4 ٛ x1 2 1 0 0 1 2 3 0 1 2 3 x x 0 1 x 0 x x4 ٛ x2 x2 3 x4 ٛ x1 x1 3 Lane Reversal in x2 mode x2 x x 1 0 x2 ٛ x1 x1 Figure 1. 3 Reversal x2 ٛ x1 2 1 0 x Lane Reversal supported modes Configuration bits: EEPROM "Lane reversal disable" bit - disables lane reversal altogether 2.
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82575 Ethernet Controller Design Guide 3.0 Ethernet Component Design Guidelines These sections provide recommendations for selecting components and connecting special pins. For 1000 BASE-T designs, the main design elements are the 82575 Gigabit Ethernet Controller, an integrated discrete or magnetics module with RJ-45 connector, an EEPROM, and a clock source. 3.
82575 Ethernet Controller Design Guide consistent from sample to sample and that measurements meet the published specifications. 3. Perform physical layer conformance testing and EMC (FCC and EN) testing in real systems. Vary temperature and voltage while performing system level tests. 3.1.2.2 Modules for 1000 BASE-T Ethernet Magnetics modules for 1000 BASE-T Ethernet are similar to those designed solely for 10/100 Mbps, except that there are four differential signal pairs instead of two.
82575 Ethernet Controller Design Guide 3.2.1 LAN Disable for 82575 Ethernet Controller Gigabit Ethernet Controller The 82575 Ethernet Controller device has three signals that can be used for disabling Ethernet functions from system BIOS. LAN0_DIS_N and LAN1_DIS_N are the separated port disable signals and DEV_OFF_N is the device disable signal. Each signal can be driven from a system output port. Choose outputs from devices that retain their values during reset.
82575 Ethernet Controller Design Guide Table 2. Strapping Options for LAN Disable Symbol Ball # Name and function LAN1_DIS_N A15 This pin is a strapping option pin always active. This pin has an internal weak pull-up resistor. In case this pin is not connected or driven hi during init time, LAN 1 is enabled. In case this pin is driven low during init time, LAN 1 function is disabled. This pin is also used for testing and scan. LAN0_DIS_N B13 This pin is a strapping option pin always active.
82575 Ethernet Controller Design Guide • Legacy Wake On LAN (magic packets) is not supported • All the initializations normally loaded from the EEPROM will be loaded by the host driver. For more information, see the 82575 Gigabit Ethernet Controller Software Developer's Manual and the 82575 EEPROM Information Guide Application Note AP-499. 3.2.2.3 SPI EEPROMs for 82575 Ethernet Controller Controller SPI EEPROMs that have been found to work satisfactorily with the 82575 device are listed in Table 4.
82575 Ethernet Controller Design Guide Table 5. 82575 Ethernet Controller EEPROM Memory Layout 0 MAC address + SW Area 0xA HW Area 0X30 PXE Area 0x40 Reserved 0x50 FW pointers FW structures PCIE/PHY/PLL/SerDes structures 3.2.3.1 EEUPDATE Intel has an MS-DOS* software utility called EEUPDATE, which can be used to program EEPROM images in development or production line environments. To obtain a copy of this program, contact your Intel representative. 3.2.
82575 Ethernet Controller Design Guide 2. A particular address range of the IOADDR register defined by the IO Base Address Register (PCIe Control Register at offset 18h or 20h). 3. The Expansion ROM Base Address Register (PCIe Control Register at offset 30h). The 82575 controls accesses to the Flash when it decodes a valid access. Note: Flash read accesses must always be assembled by the 82575 whenever the access is greater than a byte-wide access.
82575 Ethernet Controller Design Guide Note: 3.2.4.3 Sector erase by SW is not supported. In order to delete a sector, the serial (bit bang) interface should be used. FLASH Device Information While Intel does not make specific recommendations regarding FLASH devices, the following devices have been used successfully in previous designs: Manufacturer 3.
82575 Ethernet Controller Design Guide SM BCLK SM BD SM BALRT_N SM B (82575) (Configuration traffic in NCSI/ SM B M ode) NCSI_RXD [1:0] External BM C NCSI_CRS_DV NCSI_TXD[1:0] NCSI_TX_EN NCSI (82575) (All traffic in NCSI M ode and pass-thru traffic in NCSI/SM B M ode) NCSI_CLK_IN NCSI_CLK_O UT Figure 2. External BMC Connections with NC-SI and SMB The 82575 Ethernet Controller also supports the DMTF protocol.
82575 Ethernet Controller Design Guide VCC3V3 VCC1V8_SWITCHING Vout=1.8v (2.5A) 22p Y C104 X5R C102 47p Y R113 Y 75K 1 R111 Y 110K R95 R92 R109 100K Y Y 301K Y 1M C85 16 2 PGOOD SW4 15 3 ITH SW3 14 4 VFB PGND2 13 PGND1 12 SW2 11 SW1 10 PVin1 9 5 RT 6 SYNC/MODE 7 RUN/SS 8 470p X7R PVin2 SGND C66 22u Y X5R L2 1u Y C56 22u Y X5R C65 22u Y X5R 22u Y C64 Y 17 Y SVin E_PAD Y C103 560p X7R R112 Y 232K U9 R110 Y 10K <> Vout=0.
82575 Ethernet Controller Design Guide The 1.8 V rail has a lower current requirement; however, the use of a SVR is still recommended for adequate margin. Using an LVR in this application is acceptable as long as adequate margin exists in the design, and sequencing can be controlled. Figure 3 shows an example of a compact low-part -count LVR that could be used for the 1.8 V supply. VCC1V8_LINEAR VCC3V3 2 1 4 C29 22u Y R69 200 Y Vout GND R70 470 Y Adj Vin U1 Vout C30 10u Y 3 Vout=1.
82575 Ethernet Controller Design Guide Y Y Y Y W Figure 5. Proper power sequencing for 82575 Ethernet Controller Vcc power on HW operation FW operation LAN_PWR_GOOD reset Load EEPROM PE_RST_n reset Initialize FW “veto” bit on? Configure MAC and PHY Reset PHY yes Yes Initialize RMII link Reset MAC Load EEPROM Run Manageability FW Dr mode Initialize PCI-E No Platform powered ? Figure 6.
82575 Ethernet Controller Design Guide • 1.8 V must not exceed 3.3 V. • 1.0 V must not exceed 3.3 V. • 1.0 V must not exceed 1.8 V. The power supplies are all expected to ramp during a short power-up internal (approximately 20ms or better). Do not leave the device in a prolonged state were some, but not all, voltages are applied. 3.4.1.1 Using Regulators With Enable Pins The use of regulators with enable pins is very helpful in controlling sequencing. Connecting the enable of the 1.8 V regulator to 3.
82575 Ethernet Controller Design Guide logic input to the 82575 Ethernet Controller that denotes auxiliary power is available. If AUX_PWR is asserted, the 82575 Ethernet Controller device will advertise that it supports wake up from a D3cold state. The 82575 Ethernet Controller device supports both Advanced Power Management (APM) wakeup and Advanced Configuration and Power Interface (ACPI) wakeup. APM wakeup has also been known in the past as “Wake on LAN” and as “Magic Packet Wakeup”.
82575 Ethernet Controller Design Guide Internal_Power_On _Reset assertion L0s L3 PERST# deassertion Dr PERST# assertion L2 D0u L0 L1 Enable master Access PERST# assertion Write 00 to Power State PERST# assertion L0s L1 Write 11 to Power State D0a L0 D3 Figure 8. PCIe Power Management Flow/State Diagram 3.4.4.
82575 Ethernet Controller Design Guide 3.5 82575 Ethernet Controller Device Test Capability The 82575 Ethernet Controller Gigabit Ethernet Controller contains a test access port (3.3 V only) conforming to the IEEE 1149.1a-1994 (JTAG) Boundary Scan specification. To use the test access port, connect these balls to pads accessible by your test equipment. A BSDL (Boundary Scan Definition Language) file describing the 82575 Ethernet Controller device is available for use in your test environment.
82575 Ethernet Controller Design Guide 3.6.2 Smartspeed SmartSpeed is an enhancement to auto-negotiation that allows the PHY to react to network conditions that are preventing a 1000BASE-T link, such as cable problems. These problems may allow auto-negotiation to complete, but then inhibit completion of the training phase. Normally, if a 1000BASE-T link fails, the PHY returns to the autonegotiation state with the same speed settings indefinitely.
82575 Ethernet Controller Design Guide The table below summarizes link speed as function of power management state, link speed control, and gigabit speed enabling: Gigabit disable bits Power Management State Low Power Link Up (reg 25.1 & 2) Disable 1000 (reg 25.6) Disable 1000 in non-D0a (reg 25.3) 0 0 X 1 D0a 0 1 X 1 0 0 0 0 1 1 X 0 0 0 1 Non-D0a 1 3.6.
82575 Ethernet Controller Design Guide 3.6.7 Auto-Negotiation differences between PHY, SerDes and SGMII SGMII protocol includes an auto-negotiation process in order to establish the MAC PHY connection. This auto-negotiation process is not dependent on the SRDS0/ 1_SIG_DET signal, as this signal indicates the status of the PHY signal detection (usually used in Optical PHY). The following shows the outcome of this auto-negotiation process: • Link status • Speed • Duplex.
82575 Ethernet Controller Design Guide is complete, the driver must read the PHY registers to determine the resolved flow control behavior of the link and reflect these in the MAC register settings (CTRL.TFCE and CTRL.RFCE). Note: Once PHY Auto-negotiation is complete, the PHY will assert a link indication (LINK) to the MAC. Software must have set the "Set Link Up" bit in the Device Control Register (CTRL.SLU) before the MAC recognizes the LINK indication from the PHY and can consider the link to be up.
82575 Ethernet Controller Design Guide • The 82575 will put the PHY in power down unless CONNSW.ASCLR_DIS is set. In such a case the host driver is responsible for the clearing of the AUTOSENSE_EN bit According to the result of the interrupt, the software can then decide to switch to the other core. The following procedures need to be followed to actually switch between the two modes: Internal PHY-to-SerDes Transition • Disable Receiver by clearing RCTL.RXEN • Disable Transmitter by clearing TCTL.
82575 Ethernet Controller Design Guide Note that if the device is configured to provide a 50MHz NC-SI clock (via the NC-SI Output Clock EEPROM bit), then the NC-SI clock must be provided in Device Disable mode as well the device should not be disabled. Device Disable is initiated by asserting the asynchronous DEV_OFF_N pin. The DEV_OFF_N pin has an internal pull-up resistor, so that it can be left not connected to enable device operation.
82575 Ethernet Controller Design Guide Note: To avoid signal contention, all four pins are set as input pins until after EEPROM configuration has been loaded. In addition to all four pins being individually configurable as inputs or outputs, they may be configured for use as general-purpose interrupt (GPI) inputs. To act as GPI pins, the desired pins must be configured as inputs.
82575 Ethernet Controller Design Guide 4.0 Frequency Control Device Design Considerations This section provides information regarding frequency control devices, including crystals and oscillators, for use with all Intel Ethernet controllers. Several suitable frequency control devices are available; none of which present any unusual challenges in selection. The concepts documented herein are applicable to other data communication circuits, including Platform LAN Connect devices (PHYs).
82575 Ethernet Controller Design Guide 4.1.3 Programmable Crystal Oscillators A programmable oscillator can be configured to operate at many frequencies. The device contains a crystal frequency reference and a phase lock loop (PLL) clock generator. The frequency multipliers and divisors are controlled by programmable fuses. A programmable oscillator’s accuracy depends heavily on the Ethernet device’s differential transmit lines.
82575 Ethernet Controller Design Guide 5.0 Crystal Selection Parameters All crystals used with Intel Ethernet controllers are described as “AT-cut,” which refers to the angle at which the unit is sliced with respect to the long axis of the quartz stone. Table 4 lists crystals which have been used successfully in other designs (however, no particular product is recommended): Table 7. Crystal Manufacturers and Part Numbers Manufacturer Part No. RALTRON AS-25.
82575 Ethernet Controller Design Guide Note: Crystals also carry other specifications for storage temperature, shock resistance, and reflow solder conditions. Crystal vendors should be consulted early in the design cycle to discuss the application and its environmental requirements. 5.5 Calibration Mode The terms “series-resonant” and “parallel-resonant” are often used to describe crystal oscillator circuits.
82575 Ethernet Controller Design Guide An allowance of 3 pF to 7 pF accounts for lumped stray capacitance. The calculated load capacitance is 16 pF with an estimated stray capacitance of about 5 pF. Individual stray capacitance components can be estimated and added. For example, surface mount pads for the load capacitors add approximately 2.5 pF in parallel to each capacitor. This technique is especially useful if Y1, C1 and C2 must be placed farther than approximately one-half (0.5) inch from the device.
82575 Ethernet Controller Design Guide Even with a perfect support circuit, most crystals will oscillate slightly higher or slightly lower than the exact center of the target frequency. Therefore, frequency measurements (which determine the correct value for C1 and C2) should be performed with an ideal reference crystal. When the capacitive load is exactly equal to the crystal’s load rating, an ideal reference crystal will be perfectly centered at the desired target frequency. 5.11.
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82575 Ethernet Controller Design Guide 6.0 Oscillator Support The 82575 clock input circuit is optimized for use with an external crystal. However, an oscillator can also be used in place of the crystal with the proper design considerations: • The clock oscillator has an internal voltage regulator of 1.2 V to isolate it from the external noise of other circuits to minimize jitter. If an external clock is used, this imposes a maximum input clock amplitude of 1.2 V.
82575 Ethernet Controller Design Guide A low capacitance, high impedance probe (C < 1 pF, R > 500 KΩ) should be used for testing. Probing the parameters can affect the measurement of the clock amplitude and cause errors in the adjustment. A test should also be done after the probe has been removed for circuit operation. If jitter performance is poor, a lower jitter clock oscillator can be implemented. Figure 10. Reference Oscillator Circuit 1.2v VGG =0.6V 82575 VDD =3.
82575 Ethernet Controller Design Guide 7.0 Ethernet Component Layout Guidelines These sections provide recommendations for performing printed circuit board layouts. Good layout practices are essential to meet IEEE PHY conformance specifications and EMI regulatory requirements. 7.
82575 Ethernet Controller Design Guide Minimizing the amount of space needed for the Ethernet LAN interface is important because other interfaces will compete for physical space on a motherboard near the connector. The Ethernet LAN circuits need to be as close as possible to the connector. Keep silicon traces at least 1" from edge of PB (2" is preferred). Keep LAN silicon 1" - 4" from LAN connector.
82575 Ethernet Controller Design Guide Termination resistors placed within 250 mils of silicon Figure 13. Layout for Integrated Magnetics GND plane cut for High POT isolation Termination resistors placed within 250 mils of the silicon TVS Diodes for improved CDE Protection Figure 14.
82575 Ethernet Controller Design Guide 7.1.2 Crystals and Oscillators Clock sources should not be placed near I/O ports or board edges. Radiation from these devices may be coupled into the I/O ports and radiate beyond the system chassis. Crystals should also be kept away from the Ethernet magnetics module to prevent interference. 7.1.2.1 Crystal layout considerations Note: Failure to follow these guidelines could result in the 25 MHz clock failing to start.
82575 Ethernet Controller Design Guide Crystal 90 mils Capacitor 90 mils “B” Crystal Pad “A” 27pF 0402 “B” Crystal Pad Capacitor 27pF 0402 Less than 660 mils “C” Resistor 30-ohm 0402 Xtal2 Xtal1 Ethernet Controller Figure 15. Recommended Crystal Placement and Layout 7.1.3 Board Stack Up Recommendations Printed circuit boards for these designs typically have six, eight, or more layers.
82575 Ethernet Controller Design Guide 7.1.4 Differential Pair Trace Routing for 10/100/1000 Designs Trace routing considerations are important to minimize the effects of crosstalk and propagation delays on sections of the board where high-speed signals exist. Signal traces should be kept as short as possible to decrease interference from other signals, including those propagated through power and ground planes.
82575 Ethernet Controller Design Guide 7.1.4.1 Signal Termination and Coupling The four differential pairs of each port are terminated with 49.9 Ω (1% tolerance) resistors, placed near the 82575 controller. One resistor connects to the MDI+ signal trace and another resistor connects to the MDI- signal trace. The opposite ends of the resistors connect together and to ground through a single 0.1μF capacitor. The capacitor should be placed as close as possible to the 49.9 ohm resistors, using a wide trace.
82575 Ethernet Controller Design Guide 7.1.6.1 Signal Detect Each port of the 82575 controller has a Signal Detect pin for connection to optical transceivers. For designs without optical transceivers, these signals can be left unconnected because they have internal pull-up resistors. Signal Detect is not a highspeed signal and does not require special layout. 7.1.7 Routing 1.8 V to the Magnetics Center Tap The central-tap 1.8 V should be delivered as a solid supply plane (1.
82575 Ethernet Controller Design Guide • Isolate I/O signals from high-speed signals to minimize crosstalk, which can increase EMI emission and susceptibility to EMI from other signals. • Avoid routing high-speed LAN traces near other high-frequency signals associated with a video controller, cache controller, processor, or other similar devices. 7.1.
82575 Ethernet Controller Design Guide 7.1.14 Thermal Design Considerations The 82575 Gigabit Ethernet Controller contains a thermal sensor that is accessible through the SMBus. Trip points can be set in the EEPROM for the device. IcePak* and FlowTherm* models are available for the 82575 Ethernet Controller; contact your Intel representative for information. Refer to the application note: Intel® 82575 Ethernet Controller Thermal Design Considerations for more information. 7.
82575 Ethernet Controller Design Guide where the traces enter or exit the magnetics, the RJ-45 connector, and the Ethernet silicon. 6. Use of a low-quality magnetics module. 7. Re-use of an out-of-date physical layer schematic in a Ethernet silicon design. The terminations and decoupling can be different from one PHY to another. 8. Incorrect differential trace impedances. It is important to have ~100 W impedance between the two traces within a differential pair.
82575 Ethernet Controller Design Guide 8.0 Thermal Management Please see the 82575 Thermal Application Note, available on the Intel Developer site. 9.0 Reference Design Bill of Materials The bill of materials for Intel’s reference designs is available on the Intel Developer site. 10.0 Design and Layout Checklists Design and Layout checklists are available on the Intel Developer site; please contact your Intel representative to obtain these documents. 11.
