Intel NetStructure® MPCBL0001 High Performance Single Board Computer Technical Product Specification July 2005 Order Number: 273817-007
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
Contents Contents 1 Introduction.................................................................................................................................... 11 1.1 1.2 2 Features Overview ........................................................................................................................ 14 2.1 2.2 3 Document Organization ...................................................................................................... 11 Glossary........................................
Contents 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 4 E-Keying ............................................................................................................................. 44 IPMC Firmware Code ......................................................................................................... 44 IPMC Firmware Upgrade Procedure .................................................................................. 45 3.6.1 IPMC Firmware Upgrade Using KCS Interface .......
Contents 4 Connectors .................................................................................................................................... 70 4.1 4.2 4.3 5 Addressing..................................................................................................................................... 85 5.1 5.2 5.3 5.4 6 Configuration Registers ...................................................................................................... 85 5.1.
Contents 7.10 7.11 7.12 8 BIOS Setup.................................................................................................................................. 106 8.1 8.2 8.3 8.4 8.5 8.6 9 10.4 10.5 BIOS Configuration........................................................................................................... 132 BIOS Image Updates........................................................................................................
Contents 12 Thermals......................................................................................................................................138 13 Component Technology ..............................................................................................................139 14 Warranty Information ...................................................................................................................140 14.1 14.2 14.
Contents Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 8 P64H2 Interfaces........................................................................................................................ 19 Hardware Sensors...................................................................................................................... 28 SEL Events Supported by the MPCBL0001 SBC..................................
Contents 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 87 86 88 89 90 91 92 93 94 95 96 97 98 I/O Address Cross-References................................................................................................... 86 Memory Map............................................................................................................................... 87 SMBus Addresses ..................................................................
Contents Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Intel NetStructure® MPCBL0001 SBC Block Diagram............................................................... 15 Memory Ordering........................................................................................................................ 20 Hardware Management Block Diagram...................................................................................... 27 IPMC Firmware Code Process ............
Introduction Introduction 1.1 1 Document Organization This document gives technical specifications related to the Intel NetStructure® MPCBL0001 High Performance Single Board Computer. The MPCBL0001 is designed following the standards of the Advanced Telecommunications Compute Architecture (AdvancedTCA*) Design Guide for high availability, switched network computing. This document is intended for support during system product development and while sustaining a product.
Introduction Chapter 14, “Warranty Information” provides warranty information for Intel® NetStructureTM products. Chapter 15, “Customer Support” provides information on how to contact customer support. Chapter 16, “Certifications” and Chapter 17, “Agency Information—Class A” document the regulatory requirements the MPCBL0001 is designed to meet. Appendix A, “Reference Documents” provides a list of data sheets, standards, and specifications for the technology designed into the MPCBL0001.
Introduction IPMC Intelligent Platform Management Controller. ASIC in baseboard responsible for low-level system management. IPMI Intelligent Platform Management Interface. Programming model for system management. KCS Keyboard Controller Style interface. LPC Bus Los Pin Count Bus. Legacy I/O bus that replaces ISA and X-bus. See the Low Pin Count (LPC) Interface Specification. MTBF Mean Time Between Failure. A reliability measure based on the probability of failure.
Features Overview Features Overview 2.1 2 Application The Advanced Telecommunications Compute Architecture (AdvancedTCA) standards define open architecture modular computing components for carrier-grade, communications network infrastructure. The goals of the standards are to enable blade-based modular platforms to be: • • • • cost effective high-density high-availability scalable These systems use a fabric I/O network for connecting multiple, independent processor boards, I/O nodes (e.g.
Features Overview Intel NetStructure® MPCBL0001 SBC Block Diagram Figure 1. Optional Optional2.5” 2.5” Hard Hard Disk DiskDrive Drive -48V P10 IPMB-A IPMB IPMB Isolators Isolators IPMB IPMB Isolators Isolators IPMB-B Intel Intel 82802AC 82802AC (FWH0) (FWH0) Intel Intel 82802AC 82802AC (FWH1) (FWH1) SMBUS Standard Standard Microsystems Microsystems Corp. Corp.
Features Overview 2.2.1 Low Voltage Intel® Xeon™ Processor CPU-0 (U35), CPU-1 (U36) The MPCBL0001 SBC supports up to two Low Voltage Intel® Xeon™ processors (see Figure 20, “Intel NetStructure® MPCBL0001 Component Layout” on page 90 for locations). The Low Voltage Xeon processor incorporates Intel® NetBurst™ microarchitecture and a high-bandwidth Front-Side Bus, allowing performance levels that are significantly higher than previous generations of IA-32 family processors.
Features Overview 2.2.2 Chipset The Intel® E7501 chipset consists of three major components: • Intel® E7501 Memory Controller Hub (MCH) • Intel® 82801CA I/O Controller Hub 3 (ICH3) • Intel® 82870P2 64-bit PCI/PCI-X Controller Hub 2 (P64H2) See Figure 20, “Intel NetStructure® MPCBL0001 Component Layout” on page 90 for their locations. 2.2.2.
Features Overview • 16-bits wide, 66 MHz clock, 8x data transfer (octal pumped) • Supports 64-bit inbound, 32-bit outbound addressing The MCH I/O subsystems interface incorporates four hub interfaces. Each Hub interface is a pointto-point connection between the MCH and an I/O bridge/device. The various components of the chipset communicate via these connected hub interfaces: • The first hub link connects the MCH to the ICH3. • The next two hub link interfaces connect the MCH to P64H2 components.
Features Overview Note: 2.2.2.3 Performance of the IDE interface may be impacted by the DMA mode and type of DMA transfers used. Even though the BIOS automatically sets the DMA mode/type, the OS could downgrade the DMA transfer mode. Check the operating system documentation to see what DMA mode is used by default and whether it is possible to change to a higher performance DMA mode.
Features Overview 2.2.3.1 Memory Ordering Rule for the MCH Platforms based on the E7501 chipset require DDR DIMMs to be populated in matched pairs in a specific order. Start with the two DIMMs furthest from the MCH in a “fill-farthest” approach (see Figure 2). This requirement is based on the signal integrity requirements of the DDR interface. Figure 2. Memory Ordering Fill Last MCH, U22 J8 Fill First J9 J10 J11 B0894-01 2.2.4 I/O 2.2.4.
Features Overview To facilitate debug and BIOS development, SIO connections such as legacy (PS/2) keyboard/ mouse and floppy may be provided on initial board revisions. Software must not rely on the presence of these connections on future board revisions. 2.2.4.2 Real-Time Clock The MPCBL0001 SBC real-time clock is integrated into the ICH3. It is derived from a 32.768 KHz crystal with the following specifications: • • • • Frequency tolerance @ 25 ºC: ±20ppm Frequency stability: maximum of -0.
Features Overview 2.2.4.5 • • • • Host interface also compliant with the PCI-X addendum, Rev 1.0a, from 50 to 133 MHz • • • • • Full IEEE 802.
Features Overview — DMA channels (transmit, receive, command, auto-request, and auto-response) • Support for JTAG boundary scan. • Supports IP as well as other protocols; however there are currently no plans to validate protocols other than SCSI_FCP. Each Fibre Channel interface of the ISP2312 includes its own internal 16-bit RISC processor and external 7.5 ns synchronous SRAM memory for instruction code and data. Parity protection is provided on accesses to this memory.
Features Overview Flash ROM BIOS updates can be performed by an end user or a network administrator over the LAN. The system should complete booting to an OS, MS-DOS* or logon to Linux* as root user. The system should have a local copy of the flash program and the BIOS data files or have the capability to copy the flash program and BIOS data files onto a local drive via the network. The flash program has a command line interface to specify the path and the file name of the BIOS data files.
Features Overview 2.2.7 Onboard Power Supplies The main power supply rails on the MPCBL0001 SBC are powered from dual-redundant -48 V power supply inputs from the backplane power connector (P10). There are also dual redundant, limited current, make-last-break-first (MLBF) power connections. See Figure 20, “Intel NetStructure® MPCBL0001 Component Layout” on page 90 for their location. 2.2.7.1 Power Feed Fuses As required by the PICMG 3.
Features Overview The VRM controller is designed to support multiple processor core voltages selected by the voltage identification (VID) pins on the processor. Logic provided on the SBC ensures that the VRM is not enabled if the two processors request different VID codes. In addition, the VRM is disabled until all other voltage converters indicate “power good.” The voltage regulator module is designed to support up to two 43 W (TDP - Thermal Design Power) processors. Note: 2.2.7.
Hardware Management Overview 3 Hardware Management Overview The Intelligent Platform Management Controller (IPMC) is an Intel-designed baseboard management controller device manufactured by Philips Semiconductor* for Intel. The high-level architecture of the baseboard management for MPCBL0001 is represented in the block diagram below. Figure 3.
Hardware Management Overview The IPMC provides six I2C bus connections. Two are used as the redundant IPMB bus connections to the backplane while another one is used for communication with the ADM1026. The remaining buses are unused. If an IPMB bus fault or IPMC failure occurs, IPMB isolators are used to switch and isolate the backplane/system IPMB bus from the faulted SBC board. Where possible, the IPMC activates the redundant IPMB bus to re-establish system management communication to report the fault.
Hardware Management Overview Table 2. Hardware Sensors (Sheet 2 of 3) Sensor Number Sensor Type Voltage/Signals Monitored Monitored via Scanning Enabled under Power State Health LED (Green to Red) 10h Voltage 3.3 VSB ADM 1026 Power On/ Off Exceeds critical threshold 11h Voltage +5 VSB ADM 1026 Power On/ Off Exceeds critical threshold 12h +1.8 VSB ADM 1026 Power On/ Off Exceeds critical threshold 13h V BAT ADM 1026 Power On/ Off Exceeds critical threshold 14h +1.
Hardware Management Overview Table 2. Hardware Sensors (Sheet 3 of 3) Monitored via Scanning Enabled under Power State System Event IPMC Power On No change 1Ah +12 V ADM 1026 Power On Exceeds critical threshold 1Bh -12 V ADM 1026 Power On Exceeds critical threshold 1Ch CPU Core Voltage ADM 1026 Power On Exceeds critical threshold Sensor Number 83h Sensor Type System Event Voltage/Signals Monitored Health LED (Green to Red) 1Dh Voltage +1.
Hardware Management Overview Table 3. SEL Events Supported by the MPCBL0001 SBC (Sheet 1 of 4) Sensor Type Code Sensor-Specific Offset (Event Data 1, Bit 0-3) Reserved 00h - Reserved - Temperature 01h - Temperature Threshold exceeded for upper critical, upper noncritical, lower critical and lower non-critical thresholds. Refer to Table 4, “Sensor Thresholds for IPMC Firmware 1.0” on page 35 for sensor thresholds data.
Hardware Management Overview Table 3.
Hardware Management Overview Table 3. Sensor Type Critical Interrupt SEL Events Supported by the MPCBL0001 SBC (Sheet 3 of 4) Sensor Type Code Sensor-Specific Offset (Event Data 1, Bit 0-3) 13h 04h Event Remarks PCI PERR Event data 2 = Bus No. Event data 3: Byte [7:3] = Device No Byte [2:0] = Func. No 05h PCI SERR Event data 2 = Bus No. Event data 3: Byte [7:3] = Device No Byte [2:0] = Func. No 07h PCI Non-Fatal error Event data 2 = Bus No.
Hardware Management Overview Table 3.
Hardware Management Overview Table 4. Sensor Thresholds for IPMC Firmware 1.0 Sensor Name Sensor Number System Event Log, reported via CLI, SNMP, RPC, RMCP Normal Value LNR LC LNC UNC UC UNR +1.5 V 1Dh Yes +1.5 V TBD 1.43 1.45 1.55 1.57 – +2.5 V 17h Yes +2.5 V TBD 2.3 2.36 2.625 2.7 – +1.8 V 16h Yes +1.8 V TBD 1.71 1.746 1.854 1.89 – VTT DDR (+1.25 V) 15h Yes +1.25 V TBD 1.185 1.20 1.3 1.315 – +1.2 V 14h Yes +1.2 V TBD 1.14 1.176 1.224 1.
Hardware Management Overview Table 5. Sensor Thresholds for IPMC Firmware 1.2 Thresholds Sensor Name Description Sensor Number Normal Value Lower Critical Lower Noncritical Upper Noncritical Upper Critical Upper Nonrecoverable +1.5V +1.5V 1Dh 1.5 1.43 (1.45) - - 1.57 (1.54) +2.5V +2.5V 17h 2.49 2.29 (2.32) 2.35 (2.375) 2.63 (2.609) 2.69 (2.67) - +1.8V +1.8V 16h 1.79 1.71 (1.73) - - 1.88 (1.86) - VTT DDR DDR Voltage 15h 1.24 1.19 (1.16) - - 1.31 (1.29) - +1.
Hardware Management Overview Table 6. Sensor Thresholds for IPMC Firmware 1.7 and Above Thresholds Sensor Name Description Sensor Number Normal Value Lower Critical Lower Noncritical Upper Noncritical Upper Critical Upper Nonrecoverable +1.5V +1.5V 1Dh 1.5 1.43 (1.45) - - 1.57 (1.54) +2.5V +2.5V 17h 2.49 2.29 (2.32) 2.35 (2.375) 2.63 (2.609) 2.69 (2.67) - +1.8V +1.8V 16h 1.79 1.71 (1.73) - - 1.88 (1.86) - VTT DDR DDR Voltage 15h 1.24 1.19 (1.16) - - 1.31 (1.
Hardware Management Overview Table 7. Sensor Thresholds for IPMC Firmware 1.14 and Above Thresholds Sensor Name Description Sensor Number Normal Value Lower Critical Lower Noncritical Upper Noncritical Upper Critical Upper Nonrecoverable +1.5V +1.5V 1Dh 1.5 1.43 (1.45) - - 1.57 (1.54) +2.5V +2.5V 17h 2.49 2.29 (2.32) 2.35 (2.375) 2.63 (2.609) 2.69 (2.67) - +1.8V +1.8V 16h 1.79 1.71 (1.73) - - 1.88 (1.86) - VTT DDR DDR Voltage 15h 1.24 1.19 (1.16) - - 1.31 (1.
Hardware Management Overview 3.2.2 Processor Events The processor asserts IERR as the result of an internal error. A thermal trip error indicates the processor junction temperature has reached a level where permanent silicon damage may occur. Upon THERMTRIP assertion, the IPMC powers down the boards. 3.2.3 DIMM Memory Events The MCH (E7501) instructs the ICH3 to report memory parity errors via SMI#.
Hardware Management Overview Table 8 shows the PCI mapping of the component subsystem of the baseboard. Table 8.
Hardware Management Overview 3.2.6 System ACPI Power State MPCBL0001 is targeted to support ACPI functionality, with support for the sleep states S0, S4 & S5. On assertion of ICH3_SLP_S5# and ICH3_SLP_S3# GPIOs, IPMC sends out a hot-swap event message to the shelf manager requesting deactivation. On successful reception of a deactivation message from the shelf manager, the FRU enters M1 power state and remains in this state.
Hardware Management Overview Table 9. CPU Failure Behavior CPU Failure Detection CPU Identification Operational Phase POST Runtime 3.2.
Hardware Management Overview 3.3 Field Replaceable Unit (FRU) Information The FRU Information provides inventory data about the boards where the FRU Information Device is located. The part number or version number can be read through software. FRU information in the MPCBL0001 includes data describing the MPCBL0001 board as per PICMG 3.0 Specification requirements. Additional multirecords will be added for the BIOS to write CPU information, BIOS version number, and PMC information to FRU data correctly.
Hardware Management Overview 3.4 E-Keying E-Keying has been defined in the PICMG 3.0 Specification to prevent board damage, prevent misoperation, and verify fabric compatibility. The FRU data contains the board point-to-point connectivity record as described in Section 3.7.2.3 of the PICMG 3.0 Specification. Upon management power-on, the firmware sets the Fibre Channel ports to front panel by default.
Hardware Management Overview When the firmware is commanded to enter firmware (FW) update mode, the operational code uses a special branch, Software Interrupt, to jump to the FW update code in the boot block. Once in FW update mode, the update code is copied into RAM, then the FW jumps to the code in RAM to execute. The FW update code cannot execute out of flash while the flash is being updated. Figure 4.
Hardware Management Overview completed, the controller goes through a reset and boots up with the new firmware. The host processor is not reset when going through a firmware update, so the operating system and applications running on the host processor are not interrupted. Below is a step-by-step procedure on how to update the firmware: 1. Copy the FW upgrade utility and FW upgrade (Hex) file to a DOS bootable floppy disk. 2.
Hardware Management Overview 3.6.2.1 Updating MPCBL0001 Firmware To update the MPCBL0001 firmware for the Intel NetStructure® MPCBL0001 SBC, execute the following commands. 1. Copy the update utility (fwpiaupd) and the firmware image file into the same directory in the RedHat Linux host. Note: If using ftp for file transfer, use binary mode to transfer files. The firmware image file or the utility file may get corrupted if binary mode is not used. 2.
Hardware Management Overview 3.7.2 Set Fibre Channel Port Selection This command sets the Fibre Channel port routing as specified in the request data bytes. The command is available over KCS and IPMB interface. Table 14.
Hardware Management Overview 3.7.4 Get HW Fibre Channel Port Selection This command returns the current Fibre Channel port routing selection as set in the hardware. The command is available over KCS and IPMB interface SetFiberChannelPortSelection. Table 16. Get HW Fibre Channel Port Selection 7 NetFn/LUN 6 5 4 2 NetFn = 3Ah (OEM Request) Command 1 0 RsLUN Cmd = 04h Byte 1 Intel IANA number (LSB) = 57h Byte 2 Intel IANA number = 01h Byte 3 Intel IANA number (MSB) = 00h Byte 1 3.7.
Hardware Management Overview 3.7.6 Get Control State This command sets the state of a control pin. This command overrides the AUTO-state of the control pin. Refer to Table 20 on page 50 for control number information. Table 18. Get Control State 7 6 NetFn/LUN 5 4 2 1 NetFn = 3Eh (OEM Request) Command 0 RsLUN Cmd = 21h Byte 1 Control number Byte 1 Completion code Byte 2 3.7.
Hardware Management Overview 3.9 Hot-Swap Process The MPCBL0001 SBC has the ability to be hot-swapped in and out of a chassis. The onboard IPMC manages the SBC’s power-up and power-down transitions. The list below, along with Figure 6, illustrates this process. 1. Ejector latch is opened. HOT_SWAP_PB# assertion. IPMC firmware detects the assertion of this signal. 2. IPMC sends "Deactivation Request" message to CMM. M state moves from M4-> M5. 3. Board moves from M5 -> M6 if the CMM grants the request. 4.
Hardware Management Overview 3.9.1 Hot-Swap LED (DS10) The MPCBL0001 SBC supports one blue Hot Swap LED, mounted on the front panel. See Figure 14, “MPCBL0001NXX SBC Front Panel” on page 71 for its location. This LED indicates when it is safe to remove the SBC from the chassis. The on-board IPMC drives this LED to indicate the hot-swap state. Refer to Table 21, “Hot-Swap LED (DS11)” on page 52.
Hardware Management Overview 3.10 Interrupts and Error Reporting 3.10.1 Device Interrupts The Low Voltage Intel® Xeon™ processor and E7501 chipset (MCH, ICH3, P64H2) utilize a mechanism for delivering interrupts that is slightly different from, though fully compatible with, previous IA-32 system platforms. The change affects only the delivery mechanism and no changes are required to existing software.
Hardware Management Overview Table 22. Interrupt Assignments (Sheet 2 of 2) Legacy Interrupt IRQ assigned HI-B P64H2 BTINTR# PIRQC# HI-C P64H2 BTINTR# PIRQD# HI-B P64H2 Fibre Channel INTA# PB_IRQ0 Fibre Channel INTB# PB_IRQ1 HI-C P64H2 Figure 7.
Hardware Management Overview 3.10.2 Error Reporting The MCH handles error reporting from the memory subsystem. Errors consist of correctable and uncorrectable bit errors. The ECC algorithms used are capable of correcting any number of bit errors contained within a 4-bit nibble. In addition, any number of bit errors contained within two 4bit nibbles is detected. The MCH communicates these errors to the ICH3 via special cycles over the hub link interface.
Hardware Management Overview 3.11 ACPI ACPI gives the operating system direct control over the power management and Plug and Play functions of a computer. The use of ACPI with theMPCBL0001 SBC requires an operating system that provides ACPI support. ACPI features include: • Plug and Play (including bus and device enumeration) and APM support (normally contained in the BIOS).
Hardware Management Overview 3.12.1 Reset Logic The following topics describe the two types of reset requests and the boot relationships among them. The two types of reset requests available on the MPCBL0001 are: • Hard reset request (always results in a cold boot) • Soft reset request (can result in either a warm or cold boot) A hard reset request occurs whenever the processor Reset line is asserted and then deasserted. A soft reset occurs whenever an assertion occurs on the processor Init line.
Hardware Management Overview 1. The reset button is pressed (see Note below). See Section 14, “MPCBL0001NXX SBC Front Panel” on page 71 for its location. 2. A processor shutdown special cycle occurred. 3. An INIT command from Port 92h I/O register (refer to the Intel® 82801CA I/O Controller Hub 3 (ICH3-S) Datasheet for information about this register). 4. An INIT command from Port CF9h I/O register. 5. A keyboard reset command (ICH3 RCIN# signal asserted). 6.
Hardware Management Overview 3.12.5 Cold Boot Any soft reset that does not meet the configuration described in the preceding Warm Boot section is classified as a cold boot. Execution starts at the reset vector, and BIOS initializes and configures all devices, including memory subsystem, as if a hard reset had occurred. See Table 25, “Reset Actions” on page 59. During a cold boot the BIOS initializes the warm reset counter to 0x0A and clears the reset flag to 1234h.
Hardware Management Overview As the many voltages power up, each regulator produces a “power good” signal. All of these power good signals are logically OR’d (with the exception of the VRM power good) to produce the ICH3_PWROK signal input to the ICH3 as shown in Figure 8, Power Good Map. When this signal is active, it indicates all on-board power is good. Next, the VRM power good is gated with the ICH3_PWROK signal in the ICH3 to produce the processor’s power good signal input.
Hardware Management Overview Figure 9.
Hardware Management Overview 3.13 Watchdog Timers (WDTs) Figure 10, “Watchdog Timers” on page 62 shows the relationship between the three watchdog timers (WDTs) on the MPCBL0001 SBC. Figure 10. Watchdog Timers ICH3 (South Bridge) WDT #3 Strobe Host Processor(s) Strobe IPMC Strobe WDT #1 PLD WDT #2 IPMB-A Isolation Logic IPMB-B Isolation Logic B1368-02 3.13.1 WDT #1 The first WDT (WDT #1) is a hardware timer in the IPMC.
Hardware Management Overview WDT #1 can also be configured to take various actions before timing out (for example, SMI, NMI, nothing) or after timing out (for example, hard reset, power down, or power cycle). In addition, an event can be logged into the SEL whenever the watchdog timer expires. If WDT #1 expires, the IPMC is not reset. For more details on the watchdog timer commands and settings, see the IPMI Specification version 1.5. On power up, the initial state is that the IPMI WDT #1 is not running.
Hardware Management Overview 3.14 LED Status 3.14.1 Health LED The MPCBL0001 SBC supports one bicolor health LED to indicate the SBC’s health status, i.e., whether a fault or error condition has been detected on the SBC. This LED is mounted on the front faceplate and driven by the onboard IPMC. The health LED will only be driven to an error condition (red) if there is a critical or non-recoverable (major or critical in AdvancedTCA parlance) condition active on the SBC.
Hardware Management Overview 3.14.4 IDE Drive Activity LED Table 28. IDE Drive Activity LED LED Status 3.14.5 Meaning Off Normal/No disk access Green (Blinking) Disk access (read/write activity) User Programmable LEDs The MPCBL0001 SBC provides two bicolor LEDs for user-programmable functions. The LEDs can be driven to display a red, green or amber color. When these LEDs are lit, they indicate a status of a user-defined function. Table 29.
Hardware Management Overview 3.14.6 Network Link/Speed LEDs The front panel of the SBC provides two LEDs for each Ethernet connection indicating the speed and link activity for that network connection: Table 31. Network Link LEDs For Channel A : L2 / For Channel B : L6 Link LED Status Meaning Off No link Solid Green Link established Blinking Green Link with activity NOTE: Refer to Figure 14 and Figure 15 for LED (L2 and L6) placement on the Front Panel. Table 32.
Hardware Management Overview Table 33. Ethernet Controller Port State LED LED Status (L1 and L5) Meaning Off No Status Red/Green/Amber Active status of user-defined function NOTE: Refer to Figure 14 and Figure 15 for LED (L1 and L5) placement on the Front Panel. 3.14.8 Fibre Channel Port State LEDs The MPCBL0001 SBC supports two Fibre Channel port state LEDs mounted on the front faceplate. The LEDs are green and yellow. When this LED is lit, it indicates the port state of each Fibre Channel port.
Hardware Management Overview 3.15.1 Cold Reset When this command is initiated, the board will perform a hard reset as described in Section 3.12.2, “Hard Reset Request” on page 57. 3.15.2 Warm Reset When this command is initiated, the board will perform a soft reset as described in Section 3.12.3, “Soft Reset Request” on page 57. 3.15.3 Graceful Reboot This specific payload control command is implemented using system interface messaging capability and the SMS_ATN bit of the KCS status registers.
Hardware Management Overview Table 36. Returned Values from the Get Message Command Byte 3.15.
Connectors 4 Connectors Connectors along the rear edge of AdvancedTCA server blades are divided into three distinct zones, as described in Section 2.3 of the PICMG 3.0 Specification. • Zone 1 for system management and power distribution • Zone 2 for data fabric • Zone 3 for the rear transition module. As shown in Figure 13, the MPCBL0001 includes several connectors to interface with applicationspecific devices. Some of the connectors are available at the front panel.
Connectors Figure 14.
Connectors Figure 15.
Connectors Table 37. LED Descriptions LED Description Out of Service, bicolor OOS Health, bicolor IDE Drive Activity FC1 FC2 Lights when drive activity occurs.
Connectors 4.1 Backplane Connectors 4.1.1 Power Distribution Connector (Zone 1) Zone 1 consists of P10, a 34-pin Positronic header connector that provides the following signals: • • • • Note: Two -48 VDC power feeds (four signals each; eight signals total) Two IPMB ports (two signals each, four signals total) Geographic address (eight signals) 5.55 Amperes are allocated to MPCBL0001 on the -48 VDC redundant power feeds. This is equivalent to 200 Watts at the minimum input voltage (-36 VDC).
Connectors Table 39.
Connectors P[C]dxp where: P = Prefix (B=Base Interface [Gigabit Ethernet], F= Fabric Interface [Fibre Channel]) C = Channel (1-2) d = direction (Tx = Transmit, Rx = Receive) x = port number (0-1) Note: A port is two differential pairs, one Tx and one Rx p = polarity (+, -) The BG, DG, FG and HG (G for Ground) columns contain the ground shields for the four columns of differential pairs. They have been omitted from the pin out tables below for simplification.
Connectors 4.2 Front Panel Connectors 4.2.1 USB Connector (J12) MOLEX part Number: 67329-0020 The MPCBL0001 SBC has one vertical USB connector that supports USB 1.1. USB connector JX is available at the front panel, as shown in Figure 13, “MPCBL0001 SBC Connector Locations” on page 70. The figure shows its position on the board. See Table 41, “USB Connector (J12) Pin Assignments” on page 77 for pinout information. Table 41. USB Connector (J12) Pin Assignments USB CONNECTOR 4.2.
Connectors Figure 18. Serial Port Connector (J17) Optional Top Ground Tabs Shielded Modular Jack Assembly molex Optional Side Ground tabs (2 places) .512 REF. 13.00 (outside) .120 REF. 3.05 .724 REF. 18.39t .120 REF. 3.05 .120 3.05 .128 3.25 .427 10.85 .829 21.05 B0902-01 Table 42.
Connectors Figure 19.
Connectors 4.2.3 Fibre Channel Small Form-Factor Pluggable (SFP) Receptacle (J34 and J35) AMP part number: 1367073-1 The MPCBL0001 SBC has two SFP receptacles that support either the copper or fiber module interface. Fibre Channel connector J34 and J35 are available at the front panel. See Figure 13, “MPCBL0001 SBC Connector Locations” on page 70 for its position on the board. See Table 44, “Fibre Channel SFP Pin Assignments” on page 81 for pinout information. Table 43.
Connectors Table 44. Fibre Channel SFP Pin Assignments USFibre Channel Connector (J34, J35) Pin Assignments Fibre Channel SFP Optical Transceiver Module (J34, J35) Fibre Channel CONNECTOR 4.2.
Connectors Table 45. PMC Connector Pin Assignments - 32 Bit J25 82 32 Bit PCI J26 32 Bit PCI Pin Signal Signal Pin Pin Signal Signal Pin 1 TCK -12 V 2 1 +12 V TRST# 2 3 Ground INTA# 4 3 TMS TDO 4 5 INTB# INTC# 6 5 TDI Ground 6 7 BUSMODE1# +5 V 8 7 Ground PCI-RSVD 8 9 INTD# PCI-RSVD 10 9 PCI-RSVD PCI-RSVD 10 11 Ground (n/c) 3.3 Vaux 12 11 BUSMODE2# +3.3 V 12 13 CLK Ground 14 13 RST# BUSMODE3# 14 15 Ground GNT[0]# 16 15 +3.
Connectors Table 46. PMC Connector Pin Assignments - 64 Bit J27 64 Bit PCI Pin Signal Signal Pin 1 PCI-RSVD Ground 2 3 Ground C/BE[7]# 4 5 C/BE[6]# C/BE[5]# 6 7 C/BE[4]# Ground 8 9 +3.3 V (V I/O) PAR64 10 11 AD[63] AD[62] 12 13 AD[61] Ground 14 15 Ground AD[60] 16 17 AD[59] AD[58] 18 19 AD[57] Ground 20 21 +3.
Connectors 4.3 On-board Connectors 4.3.1 IDE Connector (J24) Table 47.
Addressing 5 Addressing 5.1 Configuration Registers 5.1.1 Configuration Address Register MCH CONFIG_ADDRESS I/O Address: 0x0CF8 Accessed as a Dword Default Value: 0x00000000 Access: Read/Write Size: 32 bits CONFIG_ADDRESS is a 32-bit I/O register that can be accessed only as a Dword. A byte or word reference passes through the Configuration Address Register and hub link interface HI_A onto the PCI_A bus as an I/O cycle.
Addressing CONFIG_DATA is a 32-bit read/write window into the PCI configuration space. The portion of configuration space that is referenced by CONFIG_DATA is determined by the contents of CONFIG_ADDRESS. Table 49. Configuration Data Register Bit Assignments Bit Description 31:0 5.2 Configuration Data Window (CDW): If bit 31 of CONFIG_ADDRESS is set to 1, any I/O access to the CONFIG_DATA register is mapped to configuration space pointed to by the contents of CONFIG_ADDRESS.
Addressing 5.3 Memory Map Table 51. Memory Map Memory Device Address Top of addressable memory 0xFFFF_FFFF -- Firmware Hub Devices (x2) 0xFFE0_0000 Up to 16 Mbit -- Firmware Hub Device 0 0xFFF0_0000 8 Mbit/1 MB 0xFFE0_0000 8 Mbit/1 MB -- Firmware Hub Device 1 Size ...
Addressing 5.4 IPMC Addresses The IPMC supports 6 I2C/SMB buses. IPMC buses 0 and 1 provide redundant IPMB connections. The ADM1026 device is connected to SMBus 3 and provides voltage measurement capability and additional board configuration status. Table 52.
Specifications Specifications 6 This chapter defines the MPCBL0001 operating and nonoperating environments. It also documents the procedures followed to determine the reliability of MPCBL0001. 6.1 Mechanical Specifications 6.1.1 Board Outline Figure 20 and Figure 21 are annotated illustrations of the MPCBL0001 SBC showing the locations of major components. The board dimensions are 280 mm x 322.25 mm. The board pitch is 1.2” (30.48 mm).
Specifications Figure 20. Intel NetStructure® MPCBL0001 Component Layout 280 mm IDE Connector (J24) DIMMs J16 PMC Connectors GP2 GP1 322.25 mm 350.93 mm Gigabit Ethernet MCH J23 Intel® Xeon™ Processor Intel® Xeon™ Processor P10 J18 Fibre Channel Bar code: PBA number for the board Bar code: MAC Address 1 B3215-03 NOTE: MAC Address 2 is an incremental value of MAC Address 1.
Specifications Figure 21. Intel NetStructure® MPCBL0001 Component Layout 280 mm GP 2 B A C D 322.25 mm 350.93 mm Ethernet Controller GP 1 E F MCH Fibre Channel Controller G Intel® LV XeonTM 2.0 GHz J 23 Intel® LV XeonTM 2.
Specifications 6.1.2 Backing Plate The MPCBL0001 SBC has a rugged metal backing plate that forms a single-piece face plate. This backing plate is made of 1.2 mm (0.048") steel which has been zinc post-plated to resist corrosion and rust. The solid backing plate provides PCB stiffening, enhanced EMI protection from adjacent boards, and protection during flame tests. The backing plate improves serviceability by making the SBC more durable.
Specifications Figure 22.
Specifications Figure 23.
Specifications Figure 24.
Specifications Figure 25.
Specifications 6.2 Environmental Specifications The MPCBL0001 SBC meets the board-level specifications as specified in the Intel Environmental Standards Handbook – Telco Specification Document No. A78805-01. The test methodology is a combination of Intel and NEBs test requirements with the intent that the product will pass pure system-level NEBs testing. Intel will not be completing NEBs testing on the SBC. The following table summarizes environmental limits, both operating and nonoperating. Table 53.
Specifications 6.3.1.1 Environmental Assumptions • Failure rates are based on a 40° C ambient temperature. • Applied component stress levels are 50 percent (voltage, current, and/or power). • Ground, fixed, controlled environment with an environmental adjustment factor equal to 1.0. 6.3.1.2 General Assumptions • Component failure rates are constant. • Board-to-system interconnects included within estimates. • Non-electrical components (screws, mechanical latches, labels, covers, etc.
Specifications 6.3.3 Cooling Requirements The Intel NetStructure® MPCBL0001 High Performance Single Board Computer SBC should be installed vertically in a chassis, with bottom-to-top airflow. Airflow is expected to be evenly distributed across the bottom edge of the installed MPCBL0001 blade and maintain at least 300 LFM average airflow. Most components on the MPCBL0001 blade are specified to operate with a localized ambient temperature up to 70° C and do not require heat sinks.
BIOS Features BIOS Features 7.1 7 Introduction The Intel NetStructure® MPCBL0001 High Performance Single Board Computer SBC uses an Intel/AMI BIOS, which is stored in flash memory and updated using a disk-based program. In addition to the BIOS and BIOS setup program, the flash memory contains POST and Plug and Play support. The BIOS displays a message during POST identifying the type of BIOS and a revision code. Refer to the specification update for the latest default settings. 7.
BIOS Features The utility is part of the BIOS release package and can be downloaded from the Intel web site at http://www.intel.com/design/network/products/cbp/software/bios/mpcbl0001.htm. Refer to Chapter 10, “Operating the Unit,” for more information. 7.4 Redundant BIOS Functionality MPCBL0001 hardware has two flash banks for BIOS where redundant copies are stored. BIOS bank selection logic is connected to the IPMC, and the IPMC firmware allows selection of the BIOS bank.
BIOS Features 7.6 Legacy USB Support Legacy USB support enables USB devices such as keyboards, mice, and hubs to be used even when the operating system’s USB drivers are not yet available. Legacy USB support is used to access the BIOS Setup program and install an operating system that supports USB. Legacy USB support is set to Enabled by default. Note: Legacy USB support is for keyboards, mice and hubs only.
BIOS Features 7.7.1 Language Support English is the only supported language. 7.8 Recovering BIOS Data Some types of failure can destroy the BIOS. For example, the data can be lost if a power outage occurs while the BIOS is being updated in flash memory. The BIOS can be recovered from Backup BIOS. Recovery mode is active when BIOS checksum fails and notifies the IPMC to failover to the backup BIOS. 7.
BIOS Features 7.10 Fast Booting Systems 7.10.1 Quick Boot Use of the following BIOS Setup program settings reduces the POST execution time. In the Boot Menu: • Disable Option—ROM(s) if the user configuration does not use IBA(PXE) boot, or there is no Fibre Channel drive in the system. • Disable Quiet Boot eliminates display of the logo splash screen. This could save several seconds of painting complex graphic images and changing video modes.
BIOS Features Table 56. 7.12 Supervisor and User Password Functions User Mode Password to Enter Setup Password Set Supervisor Mode Password During Boot None Any user can change all options Any user can change all options None None Supervisor and user Can change all options Based on user access level: No Access, View Only, Limited, Full Access Supervisor or user If password check option is set to Setup then no password required. Otherwise requires either supervisor or user password.
BIOS Setup 8 BIOS Setup 8.1 Introduction The BIOS Setup program can be used to view and change the BIOS settings for the computer. The BIOS Setup program is accessed by pressing the key after the Power-On Self-Test (POST) begins and before the operating system boot begins. Table 58 lists the BIOS Setup program menu features. Table 58.
BIOS Setup Table 60. Main Menu Feature Options Description AMIBIOS Version BIOS ID Build Date Displays the BIOS ID. ID Type Processor Speed Reports processor type, speed, CPUID and L2 Cache size. Count System Memory Size Size Displays system memory size. System Time Hour, minute, and second Specifies the current time. Day of week System Date 8.3 Specifies the current date. Month/day/year Advanced Menu To access this menu, select Advanced on the menu bar at the top of the screen.
BIOS Setup Table 61 describes the Advanced menu. This menu sets advanced features that are available through the chipset. Table 61. Advanced Menu Feature Options Description CPU Configuration Select to display submenu Display CPU details, Enable/Disable Hyper-Threading Technology†. IDE Configuration Select to display submenu Display the primary IDE master and primary IDE slave drive. SuperIO Configuration Select to display submenu Set the serial port 1 & 21 address/interrupt.
BIOS Setup The submenu represented in the following table is used for configuring the CPU. Table 62. CPU Configuration Submenu Feature Options Description Manufacturer Display CPU Manufacturer Brand String Display CPU Brand String Frequency Display CPU Frequency HyperThreading Technology† Enable/Disable Hyper-Threading Technology†. Disabled, Enabled NOTE: Bold text indicates default setting. 8.3.
BIOS Setup Table 63. IDE Configuration Submenu (Sheet 2 of 2) Feature Options Disabled Hard Disk Write Protect Enabled Description Enable/Disable Hard Disk device write protection. This is effective only if the device is accessed through BIOS. 0 5 10 15 IDE Detect Time Out 20 Select the time out value for detecting ATA/ATAPI device(s). 25 30 35 Host&Device ATA(PI) 80Pin Cable Detect. Host Select the mechanism for detecting 80Pin ATA(PI) Cable. NOTE: Bold text indicates default setting. 8.3.
BIOS Setup Table 64. Primary IDE Master/Slave Submenu Feature Options Description Device Display IDE device. Vendor Display IDE vendor name. Size Display IDE device size. LBA Mode Display IDE LBA Mode status. Block Mode Display IDE Block Mode status. PIO Mode Display PIO Mode status. Async DMA Display Async DMA status. Ultra DMA Display Ultra DMA-5 status. S.M.A.R.T Display S.M.A.R.T status. Not installed Type Auto CDROM Select the type of IDE device connected.
BIOS Setup 8.3.3 Floppy Configuration Submenu To access this submenu, select Advanced on the menu bar, then Floppy Configuration. Main Advanced Boot Security Exit CPU Configuration IDE Configuration Floppy Configuration SuperIO Configuration ACPI Configuration System Management Configuration Event Logging Configuration Fibre Channel Routing (PICMG) Remote Access Configuration USB Configuration PCI Configuration Table 65 shows floppy device configuration options. Table 65.
BIOS Setup 8.3.4 SuperIO Configuration Submenu To access this submenu, select Advanced on the menu bar, then SuperIO Configuration. Main Advanced Boot Security Exit CPU Configuration IDE Configuration Floppy Configuration SuperIO Configuration ACPI Configuration System Management Configuration Event Logging Configuration Fibre Channel Routing (PICMG) Remote Access Configuration USB Configuration PCI Configuration Table 66 shows SuperIO configuration options. Table 66.
BIOS Setup 8.3.5 ACPI Configuration Submenu To access this submenu, select Advanced on the menu bar, then ACPI Configuration. Main Advanced Boot Security Exit CPU Configuration IDE Configuration Floppy Configuration SuperIO Configuration ACPI Configuration Advanced ACPI Configuration System Management Configuration Event Logging Configuration Fibre Channel Routing (PICMG) Remote Access Configuration USB Configuration PCI Configuration Table 67 shows ACPI configuration options. Table 67.
BIOS Setup 8.3.5.1 Advanced ACPI Configuration Submenu To access this submenu, select Advanced on the menu bar, then ACPI Configuration. Main Advanced Boot Security Exit CPU Configuration IDE Configuration Floppy Configuration SuperIO Configuration ACPI Configuration Advanced ACPI Configuration System Management Configuration Event Logging Configuration Fibre Channel Routing (PICMG) Remote Access Configuration USB Configuration PCI Configuration Table 68 shows ACPI configuration options. Table 68.
BIOS Setup 8.3.6 System Management Configuration Submenu To access this submenu, select Advanced on the menu bar, then System Management Configuration. Main Advanced Boot Security Exit CPU Configuration IDE Configuration Floppy Configuration SuperIO Configuration ACPI Configuration System Management Configuration Event Logging Configuration Fibre Channel Routing (PICMG) Remote Access Configuration USB Configuration PCI Configuration Table 69 shows System Management configuration options. Table 69.
BIOS Setup 8.3.7 Event Logging Configuration Submenu To access this submenu, select Advanced on the menu bar, then Event Logging Configuration. Main Advanced Boot Security Exit CPU Configuration IDE Configuration Floppy Configuration SuperIO Configuration ACPI Configuration System Management Configuration Event Logging Configuration Fibre Channel Routing (PICMG) Remote Access Configuration USB Configuration PCI Configuration Table 70 shows event logging configuration options. Table 70.
BIOS Setup 8.3.8 Fibre Channel Routing (PICMG) Configuration Submenu To access this submenu, select Advanced on the menu bar, then Fibre Channel Routing (PICMG) Configuration.
BIOS Setup 8.3.9 Remote Access Configuration Submenu To access this submenu, select Advanced on the menu bar, then Remote Access Configuration. Main Advanced Boot Security Exit CPU Configuration IDE Configuration Floppy Configuration SuperIO Configuration ACPI Configuration System Management Configuration Event Logging Configuration Fibre Channel Routing (PICMG) Remote Access Configuration USB Configuration PCI Configuration Table 72 shows remote access configuration options. Table 72.
BIOS Setup 8.3.10 USB Configuration Submenu To access this submenu, select Advanced on the menu bar, then USB Configuration. Main Advanced Boot Security Exit CPU Configuration IDE Configuration Floppy Configuration SuperIO Configuration ACPI Configuration System Management Configuration Event Logging Configuration Fibre Channel Routing (PICMG) Remote Access Configuration USB Configuration PCI Configuration USB configuration options. Table 73.
BIOS Setup 8.3.10.1 USB Mass Storage Device Configuration Main Advanced Boot Security Exit CPU Configuration IDE Configuration Floppy Configuration SuperIO Configuration ACPI Configuration System Management Configuration Event Logging Configuration Fibre Channel Routing (PICMG) Remote Access Configuration USB Configuration USB Mass Storage Device Configuration Table 74.
BIOS Setup USB Configuration USB Mass Storage Device Configuration PCI Configuration The menu represented in the following table is used to configure USB options. Table 75. PCI Configuration Submenu Feature Options Disabled Onboard Fibre Channel Enabled Disabled Onboard Gigabit LAN 8.4 Enabled Description Enable/Disable Onboard Fibre Channels Option-ROM. Enable/Disable Onboard Gigabit LAN Option-ROM Boot Menu To access this menu, select Boot from the menu bar at the top of the screen.
BIOS Setup The menu represented in the following table is used to configure Boot Settings. Table 77. Boot Settings Configuration Submenu Feature Options Disabled Quick Boot Disable/Enable the BIOS to skip certain tests while booting, to decrease the time needed to boot the system. Enabled Disabled Quiet Boot Display normal POST messaged/OEM logo.
BIOS Setup Table 78. Boot Device Priority Submenu Feature Options Description Hard Drive 1st Boot Device IBA 2 Set the first boot device. IBA 1 2nd Boot Device Same options as first boot device. Set the second boot device. Last Boot Device Same options as first boot device. Set the last boot device. NOTE: A device only shows as an option if it is installed and detected by the BIOS during boot. 8.4.
BIOS Setup Table 80. OS Load Timeout Timer Submenu Feature Options Description Disabled 60sec 120 sec OS Load Timeout 150 sec Select the timeout value for OS load timer. 240 sec 480 sec 600 sec Stay On Reset OS Load Action Controls the action upon timeout. Power Off Power Cycle 8.5 Security Menu To access this menu, select Security from the menu bar at the top of the screen.
BIOS Setup The menu represented in the following table is for exiting the BIOS Setup program, saving changes, and loading and saving defaults. Table 82. Exit Menu Feature Options Description Save Changes and Exit Exit system setup after saving changes. Use this to save your configured settings to the CMOS and Flash. Discard Changes and Exit Exit system setup without saving changes. Discard Changes Discard changes without exiting. Load Optimal Defaults Load optimal default values.
Error Messages 9 Error Messages 9.1 BIOS Error Messages The following table lists the error messages. Table 83. BIOS Error Messages Error Message Note: Explanation of Error Message Timer Error This timer is based on 8254 resides in ICH-3. Error message indicates an error while programming the count register of the timer. This may indicate a problem with the timer in ICH-3 CMOS Battery Low BIOS will report this error message when status bit (RTC_REGD.Bit7) in ICH3 is low.
Error Messages 2. Clear CMOS Jumper enabled 3. MFG Jumper installed. 9.2 Port 80h POST Codes During the POST, the BIOS generates diagnostic progress codes (POST-codes) to I/O port 80h. If the POST fails, execution stops and the last POST code generated is left at port 80h. This code is useful for determining the point where an error occurred. Displaying the POST codes requires an add-in card, often called a POST card (PCI, not ISA).
Error Messages Table 85. POST Code Checkpoints (Sheet 1 of 2) Checkpoint Description 03 Disable NMI, parity, video for EGA, and DMA controllers. Initialize BIOS, POST, runtime data area. Also initialize BIOS modules on POST entry and GPNV area. Initialized CMOS as mentioned in the kernel variable. 04 Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. Verify CMOS checksum manually by reading storage area.
Error Messages Table 85. POST Code Checkpoints (Sheet 2 of 2) Checkpoint 3B 130 Description Test for total memory installed in the system. Also, check for DEL or ESC keys to limit memory test. Display total memory in the system. 3C Mid POST initialization of chipset registers. 40 Detect different devices (Parallel ports, serial ports, and coprocessor in CPU, etc.) successfully installed in the system and update the BDA, EBDA, etc.
Error Messages Table 86. DIM Code Checkpoints Checkpoint 2A Description Initializes different buses and performs the following functions: • Function 0: Reset, Detect, and Disable - Disables all device nodes, PCI devices, and PnP ISA cards. Assigns PCI bus numbers. • Function 1: Static Device Initialization - initializes all static devices that include manual configured onboard peripherals, memory and I/O decode windows in PCIPCI bridges, and noncompliant PCI devices. Reserves static resources.
Operating the Unit Operating the Unit 10.1 10 BIOS Configuration See Chapter 7, “BIOS Features,” for BIOS configuration options and Chapter 8, “BIOS Setup,” for information about using the BIOS Setup program. See Section 2.2.3.1, “Memory Ordering Rule for the MCH” on page 20 for information about installing DIMMs. 10.2 BIOS Image Updates At times, new BIOS images will be released to add additional features to the SBC. The release package contains the flash utility, which comes in two versions.
Operating the Unit 10.3.2 Saving BIOS.bin to the SBC 1. Copy the flashlnx utility and BIOS.bin to the SBC running MontaVista Carrier Grade Linux. 2. Execute “chmod +x flashlnx” to change the file attribute to executable form. 3. Execute “./flashlnx -b -zc BIOS.bin” to copy the BIOS.bin file to the FWH and CMOS. 4. Upon completion, perform a reset to ensure the new CMOS settings and BIOS are loaded. Caution: 10.3.3 To ensure that the BIOS.
Operating the Unit 10.4 Jumpers The MPCBL0001 contains several jumper posts that allow the user to configure certain options not configurable through the BIOS Setup Utility. The “Jumper Locations” figure below shows the placement of the MPCBL0001 jumpers. See Table 91, “J16 Jumper Assignments” on page 135 for the function of each jumper. Note: Figure 27. The MPCBL0001 is shipped pre-configured—jumper positions do not need to be altered.
Operating the Unit Table 90. J18 Pin Assignments Lattice* Compatible JTAG Header PS/2 Keyboard/Mouse Header 1 +3.3 VSB 2 MDAT (PS/2 mouse data) 3 TDO 4 MCLK (PS/2 mouse clock) 5 TDI (H0_SKTOCC#) 6 GND 7 ISPEN# 8 +5 V (through polyswitch) 9 Key - no pin or connection 10 KBDAT (PS/2 keyboard data) 11 TMS (H1_SKTOCC#) 12 KBCLK (PS/2 keyboard clock) 13 GND 14 Key—no pin or connection 15 TCK (WDT_EN) 16 GND NOTE: Processors must be removed before using the Lattice JTAG interface.
Operating the Unit Table 93. J40 Jumper Assignments Jumper Function J40-1 to 2 Boot block unprotected. J40-2 to 3 IPMC Boot block has been protected (Default). If user were to update the IPMC boot block, the jumper needs to be connected to 1-2. NOTE: This jumper is only applicable to the following versions of MPCBL0001 boards: • MPCBL0001F04 - TA# C55360-014 • MPCBL0001N04 - TA# C13354-013 10.
Maintenance 11 Maintenance 11.1 Supervision There are four main components that perform hardware monitoring of voltages and timers. They are listed in the table below. Table 94. Hardware Monitoring Components Component Function Monitors Intelligent Platform Management Controller WDT #1 Commands from the BIOS. If the timer expires (times out), causes a soft or hard reset. Heceta-5 (ADM1026) Analog-to-Digital Voltages: +1.2 V, +1.5 V, +1.8 V, +3.3 VSB, +5 VSB, converter VCPU, VTTDDR, +2.
Thermals 12 Thermals The pressure drop curves versus the flow rate in Figure 29 represents flow impedance of the slot This information is provided in accordance with Section 5 of the PICMG 3.0 Specification. It will aid the system integrator in using the MPCBL0001 SBC in various AdvancedTCA shelves. Figure 29. 138 Power vs.
Component Technology 13 Component Technology The main components implemented on the Intel NetStructure® MPCBL0001 High Performance Single Board Computer are listed in the table below. Table 95.
Warranty Information Warranty Information 14.
Warranty Information 14.3 For the Americas Return Material Authorization (RMA) credit requests e-mail address: requests.rma@intel.com Direct Return Authorization (DRA) repair requests e-mail address: uspss.repair@intel.com DRA on-line form: http://support.intel.com/support/motherboards/draform.htm Intel Business Link (IBL): http://www.intel.com/ibl Telephone No.: 1-800-INTEL4U or 480-554-4904 Office Hours: Monday - Friday 0700-1700 MST Winter / PST Summer 14.3.
Warranty Information If the Customer Support Group verifies that the product is defective, they will have the Direct Return Authorization/Return Material Authorization Department issue you a DRA/RMA number to place on the outer package of the product. Intel cannot accept any product without a DRA/RMA number on the package.
Customer Support 15 Customer Support 15.1 Customer Support This chapter offers technical and sales assistance information for this product. Information on returning an Intel NetStructure® product for service is in the following chapter. 15.2 Technical Support and Return for Service Assistance For all product returns and support issues, please contact your Intel product distributor or Intel Sales Representative for specific information. 15.
Certifications 16 Certifications The Intel NetStructure® MPCBL0001 High Performance Single Board Computer has the following approvals: • • • • • • UL/cUL 60950 EN/IEC 60950 EN55024 VCCI AS/NZS3548 BSMI For MPCBL0001N04 and MPCBL0001F04, all boards with the TA# C13354-010 and C55360-011 (or below) respectively have the following approvals: • EN55022 Class A • FCC CFR47 Part 15 Class A Refer to Section 17, “Agency Information—Class A” on page 145 for specific details.
Agency Information—Class A Agency Information—Class A 17.1 17 North America (FCC Class A) FCC Verification Notice This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. For questions related to the EMC performance of this product, contact: Intel Corporation 5200 N.E.
Agency Information—Class A -This equipment shall be connected directly to the DC supply system earthing electrode conductor or to a bonding jumper from an earthing terminal bar or bus to which the DC supply system earthing electrode conductor is connected.
Agency Information—Class A 17.5 Japan VCCI Class A 17.6 Korean Class A 17.
Agency Information—Class B Agency Information—Class B 18.1 18 North America (FCC Class B) FCC Verification Notice This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. For questions related to the EMC performance of this product, contact: Intel Corporation 5200 N.E.
Agency Information—Class B -This equipment shall be connected directly to the DC supply system earthing electrode conductor or to a bonding jumper from an earthing terminal bar or bus to which the DC supply system earthing electrode conductor is connected.
Agency Information—Class B 18.5 Korean Class B 18.
Safety Warnings Safety Warnings Caution: 19 Review the following precautions to avoid personal injury and prevent damage to this product or products to which it is connected. To avoid potential hazards, use the product only as specified. Read all safety information provided in the component product user manuals and understand the precautions associated with safety symbols, written warnings, and cautions before accessing parts or locations within the unit. Save this document for future reference.
Safety Warnings Warning: Avoid electric shock: Do not operate in wet, damp, or condensing conditions. To avoid electric shock or fire hazard, do not operate this product with enclosure covers or panels removed. Warning: Avoid electric shock: For units with multiple power sources, disconnect all external power connections before servicing. Warning: Power supplies must be replaced by qualified service personnel only.
Safety Warnings Pour les systèmes C.A., utilisez uniquement un câble d'alimentation avec une prise de terre et établissez toujours les connexions à une prise secteur mise à la terre. Chaque câble d'alimentation doit être connecté à un circuit terminal dédié. Pour les systèmes C.C., la protection de cette unité repose sur les coupe-circuits (surintensité) du bâtiment.
Safety Warnings ventilateur ou les conduits de l'unité. Des boucliers ou des panneaux de gestion de l'air doivent être installés dans les connecteurs inutilisés du châssis. Les spécifications environnementales peuvent varier d'un produit à un autre. Veuillez-vous reporter au manuel de l'utilisateur pour déterminer les exigences en matière de flux d'air et d'autres spécifications environnementales. Avertissement : les dissipateurs de chaleur de l'appareil peuvent être chauds lors d'un fonctionnement normal.
Safety Warnings Das Gehäuse verfügt über einen eigenen Erdungs-Verbindungsbolzen. Stellen Sie die Erdungsverbindung her, ehe Sie das Stromkabel oder Peripheriegeräte anschließen, und trennen Sie die Erdungsverbindung niemals, so lange Strom- und Peripherieverbindungen angeschlossen sind. Um die Gefahr eines durch ein Telefon oder Ethernet*-System bedingten elektrischen Schlags zu verringern, schließen Sie das Stromkabel des Geräts an, ehe Sie diese Verbindungen einrichten.
Safety Warnings Vorsicht: Lithiumbatterien. Bei unsachgemäßem Austausch oder Umgang mit Batterien besteht Explosionsgefahr. Zerlegen Sie die Batterie nicht und laden Sie diese nicht wieder auf. Entsorgen Sie die Batterie nicht durch Verbrennen. Beim Auswechseln der Batterie muss dasselbe oder ein der Händlerempfehlung gleichwertiges Modell verwendet werden (CR2032). Gebrauchte Batterien müssen entsprechend den Anweisungen des Herstellers entsorgt werden.
Safety Warnings NORME DI SICUREZZA PER LE UNITÀ MONTATE IN UN RACK. Questa unità può essere alloggiata in modo permanente in un rack. Il montaggio in rack deve essere conforme ai requisiti di resistenza fisica delle norme NEBS GR-63-CORE e NEBS GR 487.Prima di installare o rimuovere l'unità da un rack, rimuovere tutte le fonti di alimentazione e i collegamenti esterni.
Safety Warnings 19.4 Instrucciones de Seguridad Examine las instrucciones sobre condiciones de seguridad que siguen para evitar cualquier tipo de daños personales, así como para evitar perjudicar el producto o productos a los que esté conectado. Para evitar riesgos potenciales, utilice el producto únicamente en la forma especificada.
Safety Warnings Advertencia: Evite sobrecargas eléctricas, calor y riesgos de descarga eléctrica o incendio: Conecte el sistema sólo a un circuito de alimentación que tenga el régimen apropiado, según lo especificado en el manual de usuario del producto. No realice conexiones con terminales cuya capacidad no se ajuste al régimen especificado para ellos. Consulte el manual de usuario del producto para que las conexiones que realice sean las correctas.
Safety Warnings 19.
Reference Documents Reference Documents A The following documents should be available when using this specification. Documents that are not available on websites may be obtained from your IBL (Intel Business Link) account, or contact your Intel Field Sales Engineer (FSE) or Field Application Engineer (FAE). • Qlogic* ISP2312 Intelligent Fibre Channel Processor data Sheet, 83312-508-00 B, March 19, 2002 (http://www.qlogic.com/products/isp_series/isp2300.
Reference Documents • Low Pin Count (LPC) Interface Specification (http://developer.intel.com/design/chipsets/ industry/lpc.htm) • Intel® Boot Agent. (http://www.intel.com/support/network/adapter/pro100/bootagent/ manual.htm) • Intel’s AdvancedTCA product line http://developer.intel.
List of Supported Commands (IPMI v1.5 and PICMG 3.0) List of Supported Commands (IPMI v1.5 and PICMG 3.0) B Table 97. IPMI 1.5 Supported Commands (Sheet 1 of 3) IPM Device Global Commands Command NetFn* CMD IPMI 1.5 Spec Func Get Device ID App 01h 17.1 Cold Reset App 02h 17.2 Get Self Test Results App 04h 17.4 Broadcast "Get Device ID" App ? 17.9 BMC Watchdog Timer Commands Command NetFn* CMD IPMI 1.5 Spec Func Reset Watchdog Timer App 22h 21.5 Set Watchdog Timer App 24h 21.
List of Supported Commands (IPMI v1.5 and PICMG 3.0) Table 97. IPMI 1.5 Supported Commands (Sheet 2 of 3) Event Commands Command NetFn* CMD IPMI 1.5 Spec Func Set Event Receiver S/E 00h 23.1 Get Event Receiver S/E 01h 23.2 Platform Event (Event Message) S/E 02h 23.3 PEF and Alerting Commands Command NetFn* CMD IPMI 1.5 Spec Func Get PEF Capabilities S/E 10h 24.1 Arm PEF Postpone Timer S/E 11h 24.2 Set PEF Configuration Parameters S/E 12h 24.
List of Supported Commands (IPMI v1.5 and PICMG 3.0) Table 97. IPMI 1.5 Supported Commands (Sheet 3 of 3) SDR Device Commands Command NetFn* Run Initialization Agent Storage CMD 2Ch IPMI 1.5 Spec Func 27.21 SEL Device Commands Command NetFn* CMD IPMI 1.5 Spec Func Get SEL Info Storage 40h 25.2 Get SEL Allocation Info Storage 41h 25.3 Reserve SEL Storage 42h 25.4 Get SEL Entry Storage 43h 25.5 Add SEL Entry Storage 44h 25.6 Partial Add SEL Entry Storage 45h 25.
List of Supported Commands (IPMI v1.5 and PICMG 3.