Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 Product Families Datasheet - Volume One of Two September 2013 Reference Number: 329187-001
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Table of Contents 1 Overview ................................................................................................................. 11 1.1 Introduction ..................................................................................................... 11 1.1.1 Processor Feature Details ........................................................................ 14 1.1.2 Supported Technologies .......................................................................... 14 1.2 Interfaces .............
3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.2.3 AES Instructions .....................................................................................80 3.2.4 Execute Disable Bit .................................................................................81 Intel® Secure Key .............................................................................................81 Intel® OS Guard ...............................................................................................
6.9 6.10 Processor Asynchronous Sideband and Miscellaneous Signals ................................ 122 Processor Power and Ground Supplies ................................................................ 125 7 Electrical Specifications ......................................................................................... 127 7.1 Processor Signaling ......................................................................................... 127 7.1.1 System Memory Interface Signal Groups ................
10.3 10.4 Fan Power Supply [STS200C] ............................................................................ 228 10.3.1 Boxed Processor Cooling Requirements.................................................... 229 Boxed Processor Contents.................................................................................
2-42 2-43 2-44 2-45 2-46 2-47 2-48 2-49 2-50 4-1 4-2 4-3 5-1 5-2 5-3 5-4 5-5 5-6 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 9-1 9-2 9-3 9-4 9-5 9-6 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 Processor ID Construction Example...................................................................... 60 RdIAMSR() ....................................................................................................... 61 PCI Configuration Address .........................................................
1-3 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 5-1 5-2 5-3 5-4 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 8 Referenced Documents .......................................................................................22 Summary of Processor-specific PECI Commands ....................................................30 Minor Revision Number Meaning ..................................................
6-11 6-12 6-13 6-14 6-15 6-16 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 8-1 8-2 9-1 9-2 9-3 9-4 10-1 10-2 10-3 10-4 System Reference Clock (BCLK{0/1}) Signals ..................................................... 121 JTAG and TAP Signals ...................................................................................... 121 SVID Signals ..................................................................................................
Revision History Revision Number 001 Description • Initial Release Revision Date September 2013 § 10 Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 Product Families Datasheet Volume One of Two
Overview 1 Overview 1.1 Introduction The Intel® Xeon® processor E5-1600 v2/E5-2600 v2 product families datasheetVolume One provides DC electrical specifications, signal integrity, differential signaling specifications, land and signal definitions, and an overview of additional processor feature interfaces. This document is intended to be distributed as a part of the complete document which consists of two volumes. The structure and scope of the two volumes are provided in Table 1-2.
Overview Table 1-1. HCC, MCC, and LCC SKU Table Summary Die Size Low-Core Count TDP (W) Model Number Core Count 130W 2U E5-2637 v2 4 130W 1S E5-1660 v2 E5-1650 v2 6 130W 1S E5-1620 v2 4 95W 1U E5-2630 v2 6 80W 1U E5-2630 v2 E5-2620 v2 6 80W 1U E5-2609 v2 E5-2603 v2 4 60W 1U E5-2630L v2 6 Some processor features are not available on all platforms. Refer to the Intel® Xeon® Processor E5 v2 Product Family Specification Update for details of each processor SKU.
Overview • Configuration Process and Registers • Processor Integrated I/O (IIO) Configuration Registers • Processor Uncore Configuration Registers DDR3 DDR3 Intel® Xeon® Processor E5-1600 v2 Product Family on the 1 Socket Platform DDR3 Figure 1-1. Volume Structure and Scope (Sheet 2 of 2) DDR3 Table 1-2. ethernet Processor SATA DMI2 . . .
Overview 1.1.1 Processor Feature Details • Up to 12 execution cores • Each core supports two threads (Intel® Hyper-Threading Technology), up to 24 threads per socket • 46-bit physical addressing and 48-bit virtual addressing • 1 GB large page support for server applications • A 32-KB instruction and 32-KB data first-level cache (L1) for each core • A 256-KB shared instruction/data mid-level (L2) cache for each core • Up to 30 MB last level cache (LLC): up to 2.
Overview • Independent channel mode or lockstep mode • Data burst length of eight cycles for all memory organization modes • Memory DDR3 data transfer rates of 800, 1066, 1333, 1600, and 1866 MT/s • 64-bit wide channels plus 8-bits of ECC support for each channel • DDR3 standard I/O Voltage of 1.5 V and DDR3 Low Voltage of 1.
Overview • Memory thermal monitoring support for DIMM temperature via two memory signals, MEM_HOT_C{01/23}_N 1.2.2 PCI Express* • The PCI Express* port(s) are fully-compliant to the PCI Express* Base Specification, Revision 3.0 (PCIe 3.0) • Support for PCI Express* 3.0 (8.0 GT/s), 2.0 (5.0 GT/s), and 1.0 (2.5 GT/s) • Up to 40 lanes of PCI Express* interconnect for general purpose PCI Express* devices at PCIe* 3.
Overview • Power Management Event (PME) functions. • Message Signaled Interrupt (MSI and MSI-X) messages • Degraded Mode support and Lane Reversal support • Static lane numbering reversal and polarity inversion support • Support for PCIe* 3.0 atomic operation, PCIe 3.0 optional extension on atomic read-modify-write mechanism • Additional read buffers for point-point transfers.
Overview • Static lane numbering reversal support • Supports DMI2 virtual channels VC0, VC1, VCm, and VCp 1.2.4 Intel® QuickPath Interconnect (Intel® QPI) • Compliant with Intel QuickPath Interconnect v1.1 standard packet formats • Implements two full width Intel QPI ports • Full width port includes 20 data lanes and 1 clock lane • 64 byte cache-lines • Isochronous access support is not available on any CPU model containing two home agents. Note: RAS support depends on processor SKU.
Overview 1.3 Power Management Support 1.3.1 Processor Package and Core States • ACPI C-states as implemented by the following processor C-states: — Package: PC0, PC1/PC1e, PC2, PC3, PC6 (Package C7 is not supported) — Core: CC0, CC1, CC1E, CC3, CC6 (Processor Core C7 is not supported) • Enhanced Intel SpeedStep® Technology 1.3.2 System States Support • S0, S1, S3, S4, S5 1.3.
Overview 1.6 Terminology Term ASPM 20 Description Active State Power Management BMC Baseboard Management Controllers Cbo Cache and Core Box. It is a term used for internal logic providing ring interface to LLC and Core.
Overview Term Description Intel® Xeon® processor E5-1600 v2 product family Intel’s 22-nm processor design, is the follow-on to the 3rd Generation Intel® Core™ Processor Family design. It is the next generation processor for use in Intel® Xeon® processor E5-1600 v2/E5-2600 v2 product families-based platforms. Intel® Xeon® processor E5-1600 v2 product family supports workstation platforms only.
Overview Term Description SKU A processor Stock Keeping Unit (SKU) to be installed in either server or workstation platforms. Electrical, power and thermal specifications for these SKU’s are based on specific use condition assumptions. Server processors may be further categorized as Efficient Performance server, workstation and HPC SKUs.
Overview Table 1-3. Referenced Documents (Sheet 2 of 2) Document Document Number/ Location PCI Express Base Specification - Revision 2.1 and 1.1 PCI Express Base Specification - Revision 3.0 http://www.pcisig.com System Management Bus (SMBus) Specification http://smbus.org/ DDR3 SDRAM Specification http://www.jedec.org Low (JESD22-A119) and High (JESD-A103) Temperature Storage Life Specifications http://www.jedec.
Overview 24 Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 Product Families Datasheet Volume One of Two
Interfaces 2 Interfaces This chapter describes the interfaces supported by the processor. 2.1 System Memory Interface 2.1.1 System Memory Technology Support The Integrated Memory Controller (IMC) supports DDR3 protocols with four independent 64-bit memory channels with 8 bits of ECC for each channel (total of 72-bits) and supports 1 to 3 DIMMs per channel depending on the type of memory installed.
Interfaces 2.2 PCI Express* Interface This section describes the PCI Express* 3.0 interface capabilities of the processor. See the PCI Express* Base Specification for details of PCI Express* 3.0. 2.2.1 PCI Express* Architecture Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers operate unchanged. The PCI Express* configuration uses standard mechanisms as defined in the PCI Plug-and-Play specification.
Interfaces Figure 2-2. Packet Flow through the Layers Framing Sequence Number Header Date ECRC LCRC Framing Transaction Layer Data Link Layer Physical Layer 2.2.1.1 Transaction Layer The upper layer of the PCI Express* architecture is the Transaction Layer. The Transaction Layer's primary responsibility is the assembly and disassembly of Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as read and write, as well as certain types of events.
Interfaces PCI Express* extends the configuration space to 4096 bytes per-device/function, as compared to 256 bytes allowed by the Conventional PCI Specification. PCI Express* configuration space is divided into a PCI-compatible region (which consists of the first 256 bytes of a logical device's configuration space) and an extended PCI Express* region (which consists of the remaining configuration space).
Interfaces The Intel® QuickPath Interconnect has an efficient architecture allowing more interconnect performance to be achieved in real systems. It has a snoop protocol optimized for low latency and high scalability, as well as packet and lane structures enabling quick completions of transactions. Reliability, availability, and serviceability features (RAS) are built into the architecture.
Interfaces Generic PECI specification details are out of the scope of this document. What follows is a processor-specific PECI client definition, and is largely an addendum to the PECI Network Layer and Design Recommendations sections for the PECI specification. Note: The PECI commands described in this document apply primarily to the Intel® Xeon® processor E5-1600 v2/E5-2600 v2 product families.
Interfaces PECI permits writes to certain Memory Controller RAS-related registers in the processor PCI configuration space. Details are covered in Section 2.5.2.10. 2.5.2 Client Command Suite PECI command requires at least one frame check sequence (FCS) byte to ensure reliable data exchange between originator and client. The PECI message protocol defines two FCS bytes that are returned by the client to the message originator.
Interfaces Read Length: 0x08 Command: 0xf7 Figure 2-5. GetDIB() Byte # Byte Definition 2.5.2.2.2 0 1 2 3 4 Client Address Write Length 0x01 Read Length 0x08 Cmd Code 0xf7 FCS 5 6 7 8 9 Device Info Revision Number Reserved Reserved Reserved 10 11 12 13 Reserved Reserved Reserved FCS Device Info The Device Info byte gives details regarding the PECI client configuration.
Interfaces Figure 2-7. Revision Number Definition Byte# 6 7 4 3 0 Major Revision# Minor Revision# Table 2-2.
Interfaces Command: 0x01 Description: Returns the highest die temperature for addressed processor PECI client. Figure 2-8. GetTemp() Byte # Byte Definition 0 1 2 3 Client Address Write Length 0x01 Read Length 0x02 Cmd Code 0x01 4 5 6 7 FCS Temp[7:0] Temp[15:8] FCS Example bus transaction for a thermal sensor device located at address 0x30 returning a value of negative 10 counts is show in Figure 2-9. Figure 2-9. GetTemp() Example Byte # Byte Definition 2.5.2.3.
Interfaces 2.5.2.4.1 Command Format The RdPkgConfig() format is as follows: Write Length: 0x05 Read Length: 0x05 (dword) Command: 0xa1 Description: Returns the data maintained in the processor package configuration space for the PCS entry as specified by the ‘index’ and ‘parameter’ fields. The ‘index’ field contains the encoding for the requested service and is used in conjunction with the ‘parameter’ field to specify the exact data being requested. The Read Length dictates the desired data return size.
Interfaces Table 2-4. RdPkgConfig() Response Definition Response 2.5.2.5 Meaning CC: 0x91 PECI control hardware, firmware or associated logic error. The processor is unable to process the request. CC: 0x93 Pcode MCA - PECI access allowed, but PECI access cannot be completed. CC: 0x94 Pcode MCA - PECI access allowed and access completes. Will respond with the data along with the response code.
Interfaces Figure 2-11. WrPkgConfig() Note: 2.5.2.5.2 The 2-byte parameter field and 4-byte write data field defined in Figure 2-11 are sent in standard PECI ordering with LSB first and MSB last. Supported Responses The typical client response is a passing FCS, a passing Completion Code and valid data. Under some conditions, the client’s response will indicate a failure. Table 2-5. WrPkgConfig() Response Definition Response Bad Write FCS 2.5.2.
Interfaces 2.5.2.6.1 DRAM Thermal and Power Optimization Capabilities DRAM thermal and power optimization (also known as RAPL or “Running Average Power Limit”) services provide a way for platform thermal management solutions to program and access DRAM power, energy and temperature parameters. Memory temperature information is typically used to regulate fan speeds, tune refresh rates and throttle the memory subsystem as appropriate.
Interfaces Table 2-6.
Interfaces 2.5.2.6.2 DRAM Thermal Estimation Configuration Data Read/Write This feature is relevant only when activity-based DRAM temperature estimation methods are being utilized and would apply to all the DIMMs on all the memory channels.
Interfaces Figure 2-13. DRAM Rank Temperature Write Data 31 24 23 Rank# 3 Absolute Temp (in Degrees C) 16 15 Rank# 2 Absolute Temp (in Degrees C) 8 7 Rank# 1 Absolute Temp (in Degrees C) 0 Rank# 0 Absolute Temp (in Degrees C) Rank Temperature Data 15 6 5 Reserved 3 2 DIMM Index 0 Channel Index Parameter format 2.5.2.6.4 DIMM Temperature Read This feature allows the PECI host to read the temperature of all the DIMMs within a channel up to a maximum of three DIMMs.
Interfaces Figure 2-15. Ambient Temperature Reference Data 31 8 7 0 Ambient Temperature (in Degrees C) Reserved Ambient Temperature Reference Data 2.5.2.6.6 DRAM Channel Temperature Read This feature enables a PECI host read of the maximum temperature of each channel. This would include all the DIMMs within the channel and all the ranks within each of the DIMMs.
Interfaces Figure 2-17. Accumulated DRAM Energy Data 31 0 Accumulated DRAM Energy Accumulated DRAM Energy Data 15 3 Reserved 2 0 Channel Index Parameter format 2.5.2.6.8 DRAM Power Info Read This read returns the minimum, typical and maximum DRAM power settings and the maximum time window over which the power can be sustained for the entire DRAM domain and is inclusive of all the DIMMs within all the memory channels.
Interfaces Figure 2-18. DRAM Power Info Read Data 63 55 Reserved 54 48 Maximum Time Window 47 46 Reserved 32 Maximum DRAM Power DRAM_POWER_INFO (upper bits) 31 Reserved 30 16 Minimum DRAM Power 15 14 Reserved 0 TDP DRAM Power (Typical Value) DRAM_POWER_INFO (lower bits) 2.5.2.6.
Interfaces Figure 2-19. DRAM Power Limit Data 31 24 2 3 17 C o ntrol Tim e W in dow R ES ER VED 16 15 R ES ER V ED 14 DRAM Pow er Lim it Enable 0 D R A M Pow er Lim it D R A M _ PO W ER _ LIM IT D ata 2.5.2.6.10 DRAM Power Limit Performance Status Read This service allows the PECI host to assess the performance impact of the currently active DRAM power limiting modes.
Interfaces Table 2-8. Service Package Identifier Read Package Power SKU Unit Read RdPkgConfig() & WrPkgConfig() CPU Thermal and Power Optimization Services Summary (Sheet 1 of 3) Index Value (decimal) 00 30 Parameter Value (word) RdPkgConfig () Data (dword) 0x0000 CPUID Information Returns processorspecific information including CPU family, model and stepping information. 0x0001 Platform ID Used to ensure microcode update compatibility with processor.
Interfaces Table 2-8.
Interfaces Table 2-8. Service RdPkgConfig() & WrPkgConfig() CPU Thermal and Power Optimization Services Summary (Sheet 3 of 3) Index Value (decimal) Parameter Value (word) RdPkgConfig () Data (dword) WrPkgConfig () Data (dword) Description Alternate Inband MSR or CSR Access Package Power Limits for Multiple Turbo Modes 27 0x0000 N/A Power Limit 2 Data Write power limit data 2 in multiple turbo mode.
Interfaces • CPUID data: This is the equivalent of data that can be accessed through the CPUID instruction execution. It contains processor type, stepping, model and family ID information as shown in Figure 2-21. Figure 2-21.
Interfaces • CPU Microcode Update Revision: Reflects the revision number for the microcode update and power control unit firmware updates on the processor sample. The revision data is a unique 32-bit identifier that reflects a combination of specific versions of the processor microcode and PCU control firmware. Figure 2-25.
Interfaces 2.5.2.6.14 Package Power SKU Read This read allows the PECI host to access the minimum, Thermal Design Power and maximum power settings for the processor package SKU. It also returns the maximum time interval or window over which the power can be sustained. If the power limiting entity specifies a power limit value outside of the range specified through these settings, power regulation cannot be guaranteed.
Interfaces negotiated PECI bit rate. A ‘reset’ or ‘clear’ of this bit or simply not setting the “Wake on PECI” mode bit could result in a “timeout” response (completion code of 0x82) from the processor indicating that the resources required to service the command are in a low power state. Alternatively, this mode bit can also be read to determine PECI behavior in package states C3 or deeper. 2.5.2.6.
Interfaces 2.5.2.6.19 Temperature Target Read The Temperature Target Read allows the PECI host to obtain the target DTS temperature (TProchot) for PROCHOT_N assertion in degrees Celsius. This is the minimum temperature at which the processor thermal control circuit (TCC) activates. The actual temperature of TCC activation may vary slightly between processor units due to manufacturing process variations. The Temperature Target read also returns the processor TCONTROL value.
Interfaces 2.5.2.6.21 Thermal Averaging Constant Write/Read This feature allows the PECI host to control the window over which the estimated processor PECI temperature is filtered. The host may configure this window as a power of two. For example, programming a value of 5 results in a filtering window of 25 or 32 samples. The maximum programmable value is 8 or 256 samples. Programming a value of zero would disable the PECI temperature averaging feature.
Interfaces While Intel requires reading the accumulated energy data at least once every 16 seconds to ensure functional correctness, a more realistic polling rate recommendation is once every 100mS for better accuracy. This feature assumes a 150W processor. In general, as the power capability decreases, so will the minimum polling rate requirement.
Interfaces The same conversion formula used for DRAM Power Limiting (see Section 2.5.2.6.9) should be applied for encoding or programming the ‘Control Time Window’ in bits [23:17]. Figure 2-35. Power Limit Data for VCC Power Plane 31 24 RESERVED 23 Control Time Window 17 16 Clamp Mode 15 14 Power Limit Enable 0 VCC Plane Power Limit VCC Power Plane Power Limit Data 2.5.2.6.
Interfaces Figure 2-36. Package Turbo Power Limit Data 63 56 55 49 Control Time Window #2 RESERVED 48 Clamp Mode #2 47 46 Power Limit Enable #2 32 Power Limit # 2 Package Power Limit 2 31 24 RESERVED 23 17 Control Time Window #1 16 Clamp Mode #1 15 14 Power Limit Enable #1 0 Power Limit # 1 Package Power Limit 1 2.5.2.6.27 Package Power Limit Performance Status Read This service allows the PECI host to assess the performance impact of the currently active power limiting modes.
Interfaces Figure 2-38. Efficient Performance Indicator Read 0 31 Efficient Performance Cycles Efficient Performance Indicator Data 2.5.2.6.29 ACPI P-T Notify Write & Read This feature enables the processor turbo capability when used in conjunction with the PECI package RAPL or power limit.
Interfaces Bit[11] is the Read Mode bit and should be set to ‘0’ for TOR reads. The Read Mode bit can alternatively be set to ‘1’ to read the ‘Core ID’ (with associated valid bit as shown in Figure 2-40) that points to the first core that asserted the IERR. In this case bits [10:0] of the parameter field are ignored. The ‘Core ID’ read may not return valid data until at least 1 mS after the IERR assertion. Figure 2-40.
Interfaces Description: Returns the data maintained in the processor IA MSR space as specified by the ‘Processor ID’ and ‘MSR Address’ fields. The Read Length dictates the desired data return size. This command supports only qword responses. All command responses are prepended with a completion code that contains additional pass/fail status information. Refer to Section 2.5.5.2 for details regarding completion codes. 2.5.2.7.
Interfaces Figure 2-43. RdIAMSR() Note: 2.5.2.7.3 The 2-byte MSR Address field and read data field defined in Figure 2-43 are sent in standard PECI ordering with LSB first and MSB last. Supported Responses The typical client response is a passing FCS, a passing Completion Code and valid data. Under some conditions, the client’s response will indicate a failure. Table 2-10. RdIAMSR() Response Definition Response Bad FCS 2.5.2.7.
Interfaces PECI access to these registers is expected only when in-band access mechanisms are not available. Table 2-11.
Interfaces 2. The PECI host must determine the total number of machine check banks and the validity of the MCi_ADDR and MCi_MISC register contents prior to issuing a read to the machine check bank similar to standard machine check architecture enumeration and accesses. 3. The information presented in Table 2-11 is applicable to the processor only.
Interfaces Figure 2-45. RdPCIConfig() Note: The 4-byte PCI configuration address and read data field defined in Figure 2-45 are sent in standard PECI ordering with LSB first and MSB last. 2.5.2.8.2 Supported Responses The typical client response is a passing FCS, a passing Completion Code and valid data. Under some conditions, the client’s response will indicate a failure. The PECI client response can also vary depending on the address and data.
Interfaces completion code. Alternatively, reads to unimplemented or hidden registers may return a completion code of 0x90 indicating an invalid request. It is also possible that reads to function 0 of non-existent IIO devices issued prior to BIOS POST may return all ‘0’s with a passing completion code. PECI originators can access this space even prior to BIOS enumeration of the system buses. There is no read restriction on accesses to locked registers.
Interfaces 2.5.2.9.2 Supported Responses The typical client response is a passing FCS, a passing Completion Code and valid data. Under some conditions, the client’s response will indicate a failure. The PECI client response can also vary depending on the address and data. It will respond with a passing completion code if it successfully submits the request to the appropriate location and gets a response.
Interfaces AW FCS Support: Yes Description: Writes the data sent to the requested register address. Write Length dictates the desired write granularity. The command always returns a completion code indicating pass/fail status. Refer to Section 2.5.5.2 for details on completion codes. Figure 2-48.
Interfaces Table 2-14. WrPCIConfigLocal() Response Definition (Sheet 2 of 2) 2.5.2.10.3 Response Meaning CC: 0x91 PECI control hardware, firmware or associated logic error. The processor is unable to process the request. WrPCIConfigLocal() Capabilities On the processor PECI clients, the PECI WrPCIConfigLocal() command provides a method for programming certain integrated memory controller and IIO functions as described in Table 2-15.
Interfaces Table 2-16.
Interfaces to a different PECI addresses. Strapping the SOCKET_ID[1:0] pins results in the client addresses shown in Table 2-17. These package strap(s) are evaluated at the assertion of PWRGOOD (as depicted in Figure 2-49). Refer to the appropriate Platform Design Guide for recommended resistor values for establishing non-default SOCKET_ID settings. The client address may not be changed after PWRGOOD assertion, until the next power cycle on the processor.
Interfaces Table 2-18. Power Impact of PECI Commands vs. C-states (Sheet 2 of 2) Command 2.5.3.5 Power Impact WrPCIConfigLocal() May require package ‘pop-up’ to C2 state RdPCIConfig() May require package ‘pop-up’ to C2 state S-states The processor PECI client is always guaranteed to be operational in the S0 sleep state. • The Ping(), GetDIB(), GetTemp(), RdPkgConfig(), WrPkgConfig(), RdPCIConfigLocal() and WrPCIConfigLocal() will be fully operational in S0 and S1.
Interfaces 2.5.3.7.1 BMC INIT Mode The BMC INIT boot mode is used to provide a quick and efficient means to transfer responsibility for uncore configuration to a service processor like the BMC. In this mode, the socket performs a minimal amount of internal configuration and then waits for the BMC or service processor to complete the initialization. 2.5.3.7.
Interfaces The processor PECI client will not clear the semaphore that was acquired to service the request until the originator sends the ‘retry’ request in a timely fashion to successfully retrieve the response data. In the absence of any automatic timeouts, this could tie up shared resources and result in artificial bandwidth conflicts. 2.5.3.
Interfaces Table 2-20. Multi-Domain Command Code Reference (Sheet 2 of 2) Command Name Domain 0 Code Domain 1 Code WrPCIConfigLocal() 0xe5 0xe6 2.5.5 Client Responses 2.5.5.1 Abort FCS The Client responds with an Abort FCS under the following conditions: • The decoded command is not understood or not supported on this processor (this includes good command codes with bad Read Length or Write Length bytes). • Assured Write FCS (AW FCS) failure.
Interfaces Note: The codes explicitly defined in Table 2-22 may be useful in PECI originator response algorithms. Reserved or undefined codes may also be generated by a PECI client device, and the originating agent must be capable of tolerating any code. The Pass/Fail mask defined in Table 2-21 applies to all codes, and general response policies may be based on this information. Refer to Section 2.5.6 for originator response policies and recommendations. 2.5.
Interfaces 2.5.7.2 Interpretation The resolution of the processor’s Digital Thermal Sensor (DTS) is approximately 1°C, which can be confirmed by a RDMSR from the IA32_THERM_STATUS MSR where it is architecturally defined. The MSR read will return only bits [13:6] of the PECI temperature sensor data defined in Figure 2-50. PECI temperatures are sent through a configurable low-pass filter prior to delivery in the GetTemp() response data.
Technologies 3 Technologies 3.1 Intel® Virtualization Technology (Intel® VT) Intel® Virtualization Technology (Intel® VT) makes a single system appear as multiple independent systems to software. This allows multiple, independent operating systems to run simultaneously on a single system. Intel VT comprises technology components to support virtualization of platforms based on Intel architecture microprocessors and chipsets.
Technologies 3.1.
Technologies partitions in the same operating system, or there can be multiple operating system instances running on the same system – offering benefits such as system consolidation, legacy migration, activity partitioning or security. 3.1.3.
Technologies The Intel TXT platform helps to provide the authenticity of the controlling environment such that those wishing to rely on the platform can make an appropriate trust decision. The Intel TXT platform determines the identity of the controlling environment by accurately measuring and verifying the controlling software. Another aspect of the trust decision is the ability of the platform to resist attempts to change the controlling environment.
Technologies The architecture consists of six instructions that offer full hardware support for AES. Four instructions support the AES encryption and decryption, and the other two instructions support the AES key expansion. Together, they offer a significant increase in performance compared to pure software implementations. The AES instructions have the flexibility to support all three standard AES key lengths, all standard modes of operation, and even some nonstandard or future variants.
Technologies For more information on Intel Hyper-Threading Technology, see http://www.intel.com/products/ht/hyperthreading_more.htm. 3.6 Intel® Turbo Boost Technology Intel Turbo Boost Technology is a feature that allows the processor to opportunistically and automatically run faster than its rated operating frequency if it is operating below power, temperature, and current limits. The result is increased performance in multithreaded and single threaded workloads.
Technologies 3.8 Intel® Intelligent Power Technology Intel® Intelligent Power Technology conserves power while delivering advanced powermanagement capabilities at the rack, group, and data center level. Providing the highest system-level performance per watt with “Automated Low Power States” and “Integrated Power Gates”.
Technologies • Extensibility - Intel AVX has built-in extensibility for the future vector extensions: — OS context management for vector-widths beyond 256 bits is streamlined. — Efficient instruction encoding allows unlimited functional enhancements: • Vector width support beyond 256 bits • 256-bit Vector Integer processing • Additional computational and/or data manipulation primitives.
Power Management 4 Power Management This chapter provides information on the following power management topics: • ACPI States • System States • Processor Core/Package States • Integrated Memory Controller (IMC) and System Memory States • Direct Media Interface Gen 2 (DMI2)/PCI Express* Link States • Intel QuickPath Interconnect States 4.1 ACPI States Supported The ACPI states supported by the processor are described in this section. 4.1.1 System States Table 4-1. System States State 4.1.
Power Management Table 4-2.
Power Management Table 4-4. System Memory Power States (Sheet 2 of 2) State Self-Refresh Description CKE de-asserted. In this mode, no transactions are executed and the system memory consumes the minimum possible power. Self refresh modes apply to all memory channels for the processor. • IO-MDLL Off: Option that sets the IO master DLL off when self refresh occurs. • PLL Off: Option that sets the PLL off when self refresh occurs.
Power Management 4.2 Processor Core/Package Power Management While executing code, Enhanced Intel SpeedStep® Technology optimizes the processor’s frequency and core voltage based on workload. Each frequency and voltage operating point is defined by ACPI as a P-state. When the processor is not executing code, it is idle. A low-power idle state is defined by ACPI as a C-state. In general, lower power C-states have longer entry and exit latencies. 4.2.
Power Management Figure 4-1. Idle Power Management Breakdown of the Processor Cores T h re a d 0 T h re a d 1 T h re a d 0 C o r e 0 S ta te T h re a d 1 C o r e N S ta te P r o c e s s o r P a c k a g e S ta te Figure 4-2.
Power Management from the ACPI-defined processor clock control registers, referred to as P_LVLx. This method of requesting C-states provides legacy support for operating systems that initiate C-state transitions via I/O reads. For legacy operating systems, P_LVLx I/O reads are converted within the processor to the equivalent MWAIT C-state request. Therefore, P_LVLx reads do not directly result in I/O reads to the system. The feature, known as I/O MWAIT redirection, must be enabled in the BIOS.
Power Management A System Management Interrupt (SMI) handler returns execution to either Normal state or the C1/C1E state. See the Intel® 64 and IA-32 Architecture Software Developer’s Manual, Volume 3A/3B: System Programmer’s Guide for more information. While a core is in C1/C1E state, it processes bus snoops and snoops from other threads. For more information on C1E, see Section 4.2.5.2, “Package C1/C1E”. To operate within specification, BIOS must enable the C1E feature for all installed processors.
Power Management — The platform may allow additional power savings to be realized in the processor. • For package C-states, the processor is not required to enter C0 before entering any other C-state. The processor exits a package C-state when a break event is detected. Depending on the type of break event, the processor does the following: • If a core break event is received, the target core is activated and the break event message is forwarded to the target core.
Power Management Figure 4-3. Package C-State Entry and Exit C1 C0 C2 C3 4.2.5.1 C6 Package C0 The normal operating state for the processor. The processor remains in the normal state when at least one of its cores is in the C0 or C1 state or when the platform has not granted permission to the processor to go into a low power state. Individual cores may be in lower power idle states while the package is in C0. 4.2.5.
Power Management 4.2.5.3 Package C2 State Package C2 state is an intermediate state which represents the point at which the system level coordination is in progress. The package cannot reach this state unless all cores are in at least C3.
Power Management 4.2.6 Package C-State Power Specifications The table below lists the processor package C-state power specifications for various processor SKUs. For details on processor SKU information, see Table 1-1, “HCC, MCC, and LCC SKU Table Summary.”. Table 4-10.
Power Management Table 4-11. Processor Package Power Pmax TDP SKUs 175 115W (12/10-cores) 180 95W (10/8-cores) 150 95W (6/4-cores) 130 80W (6/4-cores) 110 70W (10-cores) 120 60W (6-cores) 100 LV95W (10-cores) 150 LV70W (10/8-cores) 120 LV50W (6-cores) 4.3 Pmax (W) 130W 1S WS (4-cores) 75 System Memory Power Management The DDR3 power states can be summarized as the following: • Normal operation (highest power consumption).
Power Management • Precharge power-down slow exit: In this mode the data-in DLL’s on DDR are off. Existing this mode is 3 - 5 DCLK cycles until the first command is allowed, but about 16 cycles until first data is allowed. 4.3.2 Self Refresh The Power Control Unit (PCU) may request the memory controller to place the DRAMs in self refresh state. Self refresh per channel is supported. The BIOS can put the channel in self-refresh if software remaps memory to use a subset of all channels.
Power Management The I/O buffer for an unused signal should be tristated (output driver disabled), the input receiver (differential sense-amp) should be disabled. The input path must be gated to prevent spurious results due to noise on the unused signals (typically handled automatically when input receiver is disabled). 4.4 DMI2/PCI Express* Power Management Active State Power Management (ASPM) support using L1 state, L0s is not supported.
Thermal Management Specifications 5 Thermal Management Specifications 5.1 Package Thermal Specifications The processor requires a thermal solution to maintain temperatures within operating limits. Any attempt to operate the processor outside these limits may result in permanent damage to the processor and potentially other components within the system, see Section 7.7.1, “Storage Condition Specifications.” Maintaining the proper thermal environment is key to reliable, long-term system operation.
Thermal Management Specifications The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit (TCC) activation, as indicated by PROCHOT_N (see Chapter 7, “Electrical Specifications”). Systems that implement fan speed control must be designed to use this data. Systems that do not alter the fan speed need to guarantee the case temperature meets the thermal profile specifications.
Thermal Management Specifications 5.1.2 TCASE and DTS Based Thermal Specifications To simplify compliance to thermal specifications at processor run time, the processor has added a Digital Thermal Sensor (DTS) based thermal specification. Digital Thermal Sensor reports a relative die temperature as an offset from TCC activation temperature. TCASE thermal based specifications are used for heat sink sizing and DTS based specs are used for acoustic and fan speed optimizations.
Thermal Management Specifications 5.1.3 Processor Operational Thermal Specifications Each SKU has a unique thermal profile that ensures reliable operation for the intended form factor over the processor’s service life. These specifications are based on final silicon characterization. The 130W 1S WS SKUs, which are part of the Intel® Xeon® processor E5-1600 v2 product family, are intended for single processor workstations and utilize workstation specific use conditions for reliability assumptions.
Thermal Management Specifications Table 5-1. TCase Temperature Thermal Specifications TDP (W) Model Number Core Count TLA (°C) PSICA (°C/W) Minimum TCASE (°C) Maximum TCASE (°C) 150W WS E5-2687W v2 8 39.5 0.217 5.0 72.0 130W 1U E5-2697 v2 12 56.5 0.227 5.0 86.0 E5-2690 v2 10 56.5 0.242 5.0 88.0 E5-2687W v2 E5-2667 v2 8 49.8 0.186 5.0 74.0 E5-2643 v2 6 E5-2637 v2 4 50.1 0.199 5.0 76.0 E5-1660 v2 E5-1650 v2 6 42.6 0.211 5.0 70.
Thermal Management Specifications Figure 5-1. TCase Temperature Thermal Profile 5.1.3.3 Digital Thermal Sensor (DTS) thermal profiles Each DTS thermal profile is unique to each TDP and core count combination. These TDTS profiles are fully defined by the simple linear equation: TDTS = PSIPA * P + TLA Where: PSIPA is the Processor-to-Ambient thermal resistance of the processor thermal solution. TLA is the Local Ambient temperature. P is the processor power dissipation.
Thermal Management Specifications Table 5-2. Digital Thermal Sensor (DTS) Specification Summary (Sheet 2 of 2) Core Count TLA (°C) PSIPA(°C/W) Maximum TDTS (°C) E5-2687W v2 E5-2667 v2 8 49.8 0.317 91.0 E5-2643 v2 6 49.8 0.359 96.5 E5-2637 v2 4 50.1 0.422 105.0 E5-1660 v2 E5-1650 v2 6 42.6 0.400 94.6 E5-1620 v2 4 42.6 0.480 105.0 E5-2695 v2 12 55.0 0.317 91.4 E5-2680 v2 E5-2670 v2 10 54.6 0.345 94.2 E5-2660 v2 10 52.0 0.348 85.1 E5-2650 v2 E5-2640 v2 8 52.0 0.
Thermal Management Specifications Figure 5-2. Digital Thermal Sensor DTS Thermal Profile 5.1.4 Embedded Server Thermal Profiles Network Equipment Building System (NEBS) is the most common set of environmental design guidelines applied to telecommunications equipment in the United States. Embedded server SKU’s target operation at higher case temperatures and/or NEBS thermal profiles for embedded communications server and storage form factors.
Thermal Management Specifications Power specifications are defined at all VID values found in Table 7-3. The processor may be delivered under multiple VIDs for each frequency. Implementation of a specified thermal profile should result in virtually no TCC activation. Failure to comply with the specified thermal profile will result in increased probability of TCC activation and may incur measurable performance loss.
Thermal Management Specifications Figure 5-3. Embedded Case Temperature Thermal Profile 5.1.4.2 Embedded Digital Thermal Sensor (DTS) thermal profiles The thermal solution is expected to be developed in accordance with the Tcase thermal profile. Operational compliance monitoring of thermal specifications and fan speed modulation may be done via the DTS based thermal profile. Each DTS thermal profile is unique to each TDP and core count combination.
Thermal Management Specifications up to Tcontrol is permitted at all power levels. Compliance to the DTS profile is required for any temperatures exceeding Tcontrol. Table 5-4. Embedded DTS Thermal Specifications TDP (W) Model Number Core Count TLA (°C) TLA-ST (°C) PSIPA (°C/W) Nominal Maximum TDTS (°C) Short-Term Maximum TDTS (°C) LV95W E5-2658 v2 10 51 66 0.336 82.9 97.9 10 49 64 0.489 83.2 98.2 LV70W E5-2648L v2 LV70W E5-2628L v2 8 49 64 0.503 84.2 99.
Thermal Management Specifications Figure 5-5. Case Temperature (TCASE) Measurement Location Notes: 1. Figure is not to scale and is for reference only. 2. This is an example for package size 52.5 x 45 mm. 3. B1: Max = 52.57 mm, Min = 52.43 mm. 4. B2: Max = 45.07 mm, Min = 44.93 mm. 5. C1: Max = 43.1 mm, Min = 42.9 mm. 6. C2: Max = 42.6 mm, Min = 42.4 mm. 7. C3: Max = 2.35 mm, Min = 2.15 mm. 5.2 Processor Core Thermal Features 5.2.
Thermal Management Specifications reduced frequency and voltage results in a reduction to the processor power consumption. The second method (clock modulation) reduces power consumption by modulating (starting and stopping) the internal processor core clocks. The processor intelligently selects the appropriate TCC method to use on a dynamic basis. BIOS is not required to select a specific method. The Adaptive Thermal Monitor feature must be enabled for the processor to be operating within specifications.
Thermal Management Specifications SVID/frequency points. Transition of the SVID code will occur first, to insure proper operation once the processor reaches its normal operating frequency. Refer to Figure 5-6 for an illustration of this ordering. Figure 5-6. Frequency and Voltage Ordering 5.2.2.2 Clock Modulation Clock modulation is performed by alternately turning the clocks off and on at a duty cycle specific to the processor (factory configured to 37.5% on and 62.5% off for TM1).
Thermal Management Specifications Demand mode, the duty cycle of the clock modulation is programmable via bits 3:0 of the same IA32_CLOCK_MODULATION MSR. In On-Demand mode, the duty cycle can be programmed from 6.25% on / 93.75% off to 93.75% on / 6.25% off in 6.25% increments.
Thermal Management Specifications asserted, all processor supplies (VCC, VTTA, VTTD, VSA, VCCPLL, VCCD) must be removed within the timeframe provided. The temperature at which THERMTRIP_N asserts is not user configurable and is not software visible. 5.2.6 Integrated Memory Controller (IMC) Thermal Features 5.2.6.
Thermal Management Specifications to zero, then the processor ignores all external assertions of MEM_HOT_{C01/C23}_N signals (in effect they become outputs). • Output Function: The output behavior of the MEM_HOT_{C01/C23}_N signals supports Level mode. In this mode, MEM_HOT_{C01/C23}_N event temperatures are programmable via TEMP_OEM_HI, TEMP_LOW, TEMP_MID, and TEMP_HI threshold settings in the iMC.
Thermal Management Specifications 116 Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 Product Families Datasheet Volume One of Two
Signal Descriptions 6 Signal Descriptions This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category. 6.1 System Memory Interface Signals Table 6-1. Memory Channel DDR0, DDR1, DDR2, DDR3 Signal Name DDR{0/1/2/3}_BA[2:0] Description Bank Address. Defines the bank which is the destination for the current Activate, Read, Write, or Precharge command. DDR{0/1/2/3}_CAS_N Column Address Strobe.
Signal Descriptions Table 6-2. Memory Channel Miscellaneous Signal Name Description DDR_RESET_C01_N DDR_RESET_C23_N System memory reset: Reset signal from processor to DRAM devices on the DIMMs. DDR_RESET_C01_N is used for memory channels 0 and 1 while DDR_RESET_C23_N is used for memory channels 2 and 3. DDR_SCL_C01 DDR_SCL_C23 SMBus clock for the dedicated interface to the serial presence detect (SPD) and thermal sensors (TSoD) on the DIMMs.
Signal Descriptions Table 6-4. PCI Express* Port 2 Signals (Sheet 2 of 2) Signal Name Table 6-5. Description PE2D_RX_DN[15:12] PE2D_RX_DP[15:12] PCIe Receive Data Input PE2A_TX_DN[3:0] PE2A_TX_DP[3:0] PCIe Transmit Data Output PE2B_TX_DN[7:4] PE2B_TX_DP[7:4] PCIe Transmit Data Output PE2C_TX_DN[11:8] PE2C_TX_DP[11:8] PCIe Transmit Data Output PE2D_TX_DN[15:12] PE2D_TX_DP[15:12] PCIe Transmit Data Output PCI Express* Port 3 Signals Signal Name Table 6-6.
Signal Descriptions Table 6-6. PCI Express* Miscellaneous Signals (Sheet 2 of 2) Signal Name Description PCI Express* Hot-Plug SMBus Data: Provides PCI Express* hotplug support via a dedicated SMBus interface. Requires an external general purpose input/output (GPIO) expansion device on the platform. PEHPSDA 6.3 DMI2/PCI Express* Port 0 Signals Table 6-7.
Signal Descriptions 6.5 PECI Signal Table 6-10. PECI Signals Signal Name PECI 6.6 Description PECI (Platform Environment Control Interface) is the serial sideband interface to the processor and is used primarily for thermal, power and error management. Details regarding the PECI electrical specifications, protocols and functions can be found in the Platform Environment Control Interface Specification. System Reference Clock Signals Table 6-11.
Signal Descriptions 6.8 Serial VID Interface (SVID) Signals Table 6-13. SVID Signals SVIDALERT_N 6.9 Serial VID alert. SVIDCLK Serial VID clock. SVIDDATA Serial VID data out. Processor Asynchronous Sideband and Miscellaneous Signals Table 6-14. Processor Asynchronous Sideband Signals (Sheet 1 of 3) Signal Name Description BIST_ENABLE BIST Enable Strap. Input which allows the platform to enable or disable built-in self test (BIST) on the processor.
Signal Descriptions Table 6-14. Processor Asynchronous Sideband Signals (Sheet 2 of 3) Signal Name Description Memory throttle control. MEM_HOT_C01_N and MEM_HOT_C23_N signals have two modes of operation – input and output mode. MEM_HOT_C01_N MEM_HOT_C23_N Input mode is externally asserted and is used to detect external events such as VR_HOT# from the memory voltage regulator and causes the processor to throttle the appropriate memory channels.
Signal Descriptions Table 6-14. Processor Asynchronous Sideband Signals (Sheet 3 of 3) Signal Name Description SOCKET_ID[1:0] Socket ID Strap. Socket identification configuration straps for establishing the PECI address, Intel® QPI Node ID, and other settings. This signal is used in combination with FRMAGENT to determine whether the socket is a legacy socket, bootable firmware agent is present, and DMI links are used in PCIe* mode (instead of DMI2 mode).
Signal Descriptions Table 6-15. Miscellaneous Signals Signal Name 6.10 Description IVT_ID_N This output can be used by the platform to determine if the installed processor is an Intel® Xeon® processor E5-1600 v2 product family, Intel® Xeon® processor E5-2600 v2 product family or Intel® Xeon® processor E51600/E5-2600 product families. This is pulled to ground on the processor package.This signal is also used by the VCCPLL and VTT rails to switch their output voltage to support future processors.
Signal Descriptions Table 6-16. Power and Ground Signals (Sheet 2 of 2) Signal Name VSA Description Variable power supply for the processor system agent units. These include logic (non-I/O) for the integrated I/O controller, the integrated memory controller (iMC), the Intel® QPI agent, and the Power Control Unit (PCU). The output voltage of this supply is selected by the processor, using the serial voltage ID (SVID) bus. Note: VSA has a Vboot setting of 0.9V. Refer to the compatible VR12.
Electrical Specifications 7 Electrical Specifications 7.1 Processor Signaling The processor includes 2011 lands, which use various signaling technologies. Signals are grouped by electrical characteristics and buffer type into various signal groups.
Electrical Specifications 7.1.5 Platform Environmental Control Interface (PECI) PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external system management logic and thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature.
Electrical Specifications Clock multiplying within the processor is provided by the internal phase locked loop (PLL), which requires a constant frequency BCLK{0/1}_DP, BCLK{0/1}_DN input, with exceptions for spread spectrum clocking. DC specifications for the BCLK{0/1}_DP, BCLK{0/1}_DN inputs are provided in Table 7-17. These specifications must be met while also meeting the associated signal quality specifications outlined in Section 7.9. 7.1.6.
Electrical Specifications Table 7-1. Power and Ground Lands (Sheet 2 of 2) Power and Ground Lands 7.1.9.2 Number of Lands Comments VCCD_01 VCCD_23 51 Each VCCD land is connected to a switchable 1.50 V and 1.35 V supply, provide power to the processor DDR3 interface. These supplies also power the DDR3 memory subsystem. VCCD is also controlled by the SVID Bus. VCCD is the generic term for VCCD_01, VCCD_23. VTTA 14 VTTA lands must be supplied by a fixed 1.0V supply.
Electrical Specifications • SetVID_fast (10 mV/µs for VSA/VCCD), • SetVID_slow (2.5 mV/µs for VSA/VCCD), and • Slew Rate Decay (downward voltage only and it’s a function of the output capacitance’s time constant) commands. Table 7-3 and Table 7-20 includes SVID step sizes and DC shift ranges. Minimum and maximum voltages must be maintained as shown in Table 7-11. The VRM or EVRD utilized must be capable of regulating its output to the value defined by the new VID. The compatible VR12.
Electrical Specifications The VR may change its configuration to meet the processor’s power needs with greater efficiency. For example, it may reduce the number of active phases, transition from CCM (Continuous Conduction Mode) to DCM (Discontinuous Conduction Mode) mode, reduce the switching frequency or pulse skip, or change to asynchronous regulation. For example, typical power states are 00h = run in normal mode; a command of 01h= shed phases mode, and an 02h=pulse skip.
Electrical Specifications Table 7-2. SVID Address Usage (Sheet 2 of 2) PWM Address (HEX) Processor 02 VCCD_01 03 +1 not used 04 VCCD_23 05 +1 not used Notes: 1. Check with VR vendors for determining the physical address assignment method for their controllers. 2. VR addressing is assigned on a per voltage rail basis. 3. Dual VR controllers will have two addresses with the lowest order address, always being the higher phase count. 4.
Electrical Specifications Table 7-3. VR12.0 Reference Code Voltage Identification (VID) (Sheet 2 of 2) HEX VCC, VSA, VCCD HEX VCC, VSA, VCCD HEX VCC, VSA, VCCD HEX VCC, VSA, VCCD HEX VCC, VSA, VCCD HEX VCC, VSA, VCCD 4F 0.64000 72 0.81500 95 0.99000 B8 1.16500 DB 1.34000 FE 1.51500 50 0.64500 73 0.82000 96 0.99500 B9 1.17000 DC 1.34500 FF 1.52000 51 0.65000 74 0.82500 97 1.00000 BA 1.17500 DD 1.35000 52 0.65500 75 0.83000 98 1.00500 BB 1.18000 DE 1.
Electrical Specifications Table 7-4. Signal Description Buffer Types (Sheet 2 of 2) Signal PCI Express* PCI Express* interface signals. These signals are compatible with PCI Express 3.0 Signalling Environment AC Specifications and are AC coupled. The buffers are not 3.3-V tolerant. Refer to the PCIe specification. Reference Voltage reference signal. SSTL Source Series Terminated Logic (JEDEC SSTL_15) 1. Table 7-5. Description Qualifier for a buffer type.
Electrical Specifications Table 7-5.
Electrical Specifications Table 7-5. Signal Groups (Sheet 3 of 3) Differential/Single Ended Signals1 Buffer Type Processor Asynchronous Sideband Signals CMOS1.0v Input BIST_ENABLE BMCINIT FRMAGENT PWRGOOD PMSYNC RESET_N SAFE_MODE_BOOT SOCKET_ID[1:0] TXT_AGENT TXT_PLTEN Open Drain CMOS Input/Output CAT_ERR_N MEM_HOT_C{01/23}_N PROCHOT_N Open Drain CMOS Output ERROR_N[2:0] THERMTRIP_N Single ended Miscellaneous Signals N/A IVT_ID_N SKTOCC_N Output Power/Other Signals 1. 2. Table 7-6.
Electrical Specifications 7.3 Power-On Configuration (POC) Options Several configuration options can be configured by hardware. The processor samples its hardware configuration at reset, on the active-to-inactive transition of RESET_N, or upon assertion of PWRGOOD (inactive-to-active transition). For specifics on these options, please refer to Table 7-7. The sampled information configures the processor for subsequent operation.
Electrical Specifications Table 7-8. 7.
Electrical Specifications 7.6 Flexible Motherboard Guidelines (FMB) The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the processor will have over certain time periods. The values are only estimates and actual specifications for future processors may differ. Processors may or may not have specifications equal to the FMB value in the foreseeable future. System designers should meet the FMB values to ensure their systems will be compatible with future processors. 7.
Electrical Specifications device storage conditions for a sustained period of time. At conditions outside sustained limits, but within absolute maximum and minimum ratings, quality & reliability may be affected. Table 7-10. Storage Condition Ratings Symbol Parameter Min Max Unit Tabsolute storage The minimum/maximum device storage temperature beyond which damage (latent or otherwise) may occur when subjected to for any length of time.
Electrical Specifications Table 7-11. Voltage Specification (Sheet 2 of 2) Symbol Parameter VVID_STEP (Vcc, Vsa, Vccd) VID step size during a transition VCCPLL PLL Voltage VCCD (VCCD_01, VCCD_23) Voltage Plane Min Typ Max 5.0 Unit Notes1 mV 10 VCCPLL 0.955*VCCPLL_TYP 1.7 1.045*VCCPLL_TYP V 11, 12, 13, 17 I/O Voltage for DDR3 (Standard Voltage) VCCD 0.95*VCCD_TYP 1.5 1.05*VCCD_TYP V 11, 13, 14, 16, 17 VCCD (VCCD_01. VCCD_23) I/O Voltage for DDR3L (Low Voltage) VCCD 0.
Electrical Specifications Table 7-12. Processor Current Specifications Parameter Symbol and Definition Notes1 TDC (A) Max (A) ITT I/O Termination Supply, Processor Current on VTTA/VTTD 20 24 ISA System Agent Supply, Processor Current on VSA 20 24 3 4 3 4 ICCPLL PLL Supply, Processor Current on VCCPLL 2 2 ICCD_S3 Total processor current on VCCD_01/VCCD_23 in System S3 Standby State -- 0.
Electrical Specifications Table 7-13. Processor VCC Static and Transient Tolerance ICC (A) VCC_MAX (V) VCC_TYP (V) VCC_MIN (V) Notes 0 VID + 0.015 VID - 0.000 VID - 0.015 1,2,3,4,5,6 5 VID + 0.011 VID - 0.004 VID - 0.019 1,2,3,4,5,6 10 VID + 0.007 VID - 0.008 VID - 0.023 1,2,3,4,5,6 15 VID + 0.003 VID - 0.012 VID - 0.027 1,2,3,4,5,6 19 VID + 0.000 VID - 0.015 VID - 0.030 1,2,3,4,5,6 25 VID - 0.005 VID - 0.020 VID - 0.035 1,2,3,4,5,6 30 VID - 0.009 VID - 0.024 VID - 0.
Electrical Specifications 4. 5. 6. Figure 7-3. and VSS_VCC_SENSE lands. Refer to the compatible VR12.0 PWM controller for loadline guidelines and VR implementation details. The Vcc_min and Vcc_max loadlines represent static and transient limits. Please see Chapter 6 for Vcc Overshoot specifications. The Adaptive Loadline Positioning slope is 0.8 mΩ. For Icc ranges, reference Table 7-12, “Processor Current Specifications.
Electrical Specifications 7.8.2 Die Voltage Validation Core voltage (VCC) overshoot events at the processor must meet the specifications in Table 7-14 when measured across the VCC_SENSE and VSS_VCC_SENSE lands. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope. Figure 7-4. Load Current Versus Time Notes: 1. The peak current for any 5 second sample does not exceed Icc_max. 2.
Electrical Specifications Figure 7-5. VCC Overshoot Example Waveform VOS_MAX Voltage [V] VID + VOS_MAX VccMAX (I1) TOS_MAX 0 5 10 15 20 25 30 Time [us] Notes: 1. VOS_MAX is the measured overshoot voltage. 2. TOS_MAX is the measured time duration above VccMAX(I1). 3. Istep: Load Release Current Step, for example, I2 to I1, where I2 > I1. 4. VccMAX(I1) = VID - I1*RLL + 15mV 7.8.3 Signal DC Specifications DC specifications are defined at the processor pads, unless otherwise noted.
Electrical Specifications Table 7-15.
Electrical Specifications 11. DRAM_PWR_OK_C{01/23} must have a maximum of 30 ns rise or fall time over VCCD * 0.55 +300 mV and -200 mV and the edge must be monotonic. 12. The DDR01/23_RCOMP error tolerance is ±15% from the compensated value. 13. DRAM_PWR_OK_C{01/23}: Data Scrambling must be enabled for production environments. Disabling Data scrambling can be used for debug and testing purposes only. Running systems with Data Scrambling off will make the configuration out of specification.
Electrical Specifications 8. For Vin between 0 and Vih. Table 7-18. SMBus DC Specifications Symbol Parameter Min VIL Input Low Voltage VIH Input High Voltage 0.7*VTT VHysteresis Hysteresis 0.1*VTT VOL Output Low Voltage RON Buffer On Resistance IL Leakage Current Max Units 0.3*VTT V V V 0.2*VTT Output Edge Rate (50 ohm to VTT, between VIL and VIH) Notes V 4 14 Ω 50 200 μA 0.05 0.6 V/ns Table 7-19.
Electrical Specifications Table 7-20. Serial VID Interface (SVID) DC Specifications (Sheet 2 of 2) Symbol IIL Parameter Min Input Leakage Current +/-50 Input Edge Rate Signal: SVIDALERT_N 0.05 Output Edge Rate (50 ohm to VTT) 0.20 Typ Max ±200 1.5 Units Notes μA 3,4 V/ns 5, 6 V/ns 5 Notes: 1. VTT refers to instantaneous VTT. 2. Measured at 0.31*VTT 3. Vin between 0V and VTT 4. These are measured between VIL and VIH. 5.
Electrical Specifications Table 7-22. Miscellaneous Signals DC Specifications Symbol Parameter Min Typical Max Units Notes 1.10 1.80 V 1 0 μA 1, 3 IVT_ID_N Signal VO_ABS_MAX Output Absolute Max Voltage IO Output Current SKTOCC_N Signal VO_ABS_MAX Output Absolute Max Voltage IOMAX Output Max Current 3.30 3.50 V 1 1 mA 2 Notes: 1. IVT_ID_N land is pulled to ground on the package. 7.8.3.
Electrical Specifications Figure 7-6. BCLK{0/1} Differential Clock Crosspoint Specification 650 Crossing Point (mV) 600 550 550 mV 500 550 + 0.5 (VHavg - 700) 450 400 250 + 0.5 (VHavg - 700) 350 300 250 250 mV 200 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg (mV) Figure 7-7. BCLK{0/1} Differential Clock Measurement Point for Ringback T STABLE VRB-Differential VIH = +150 mV VRB = +100 mV 0.0V VRB = -100 mV VIL = -150 mV REFCLK + Figure 7-8.
Electrical Specifications 7.9 Signal Quality Data transfer requires the clean reception of data signals and clock signals. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage swings will adversely affect system timings. Ringback and signal non-monotonicity cannot be tolerated since these phenomena may inadvertently advance receiver state machines.
Electrical Specifications 7.9.5 Overshoot/Undershoot Tolerance Overshoot (or undershoot) is the absolute value of the maximum voltage above or below VSS, see Figure 7-9. The overshoot/undershoot specifications limit transitions beyond VCCD or VSS due to the fast signal edge rates. The processor can be damaged by single and/or repeated overshoot or undershoot events on any input, output, or I/O buffer if the charge is large enough (that is, if the over/undershoot is great enough).
Electrical Specifications The specification provided in the table shows the maximum pulse duration allowed for a given overshoot/undershoot magnitude at a specific activity factor. Each table entry is independent of all others, meaning that the pulse duration reflects the existence of overshoot/undershoot events of that magnitude ONLY. A platform with an overshoot/undershoot that just meets the pulse duration for a specific magnitude where the AF < 0.
Electrical Specifications Table 7-24. Processor Sideband Signal Group Overshoot/Undershoot Tolerance Absolute Maximum Overshoot (V) Absolute Maximum Undershoot (V) Pulse Duration (ns) AF=0.1 Pulse Duration (ns) AF=0.01 1.3335 V 0.2835 V 3 ns 5 ns 1.2600 V 0.210 V 5 ns 5 ns Figure 7-9.
Electrical Specifications 158 Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 Product Families Datasheet Volume One of Two
Processor Land Listing 8 Processor Land Listing This chapter provides sorted land list in Section 8.1 and Section 8.2. Table 8-1 is a listing of all processor lands ordered alphabetically by land name. Table 8-2 is a listing of all processor lands ordered by land number. 8.1 Listing by Land Name Table 8-1. Land Name (Sheet 1 of 50) Land Name Table 8-1. Land Name (Sheet 2 of 50) Land No. Buffer Type Direction DDR0_CKE[1] CM18 SSTL O I DDR0_CKE[2] CH20 SSTL O CP18 SSTL O Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 3 of 50) Land No. Buffer Type Direction Table 8-1. Land Name (Sheet 4 of 50) Land Name Land No.
Processor Land Listing Table 8-1. Land Name (Sheet 5 of 50) Land Name Land No. Buffer Type Direction Table 8-1. Land Name (Sheet 6 of 50) Land Name Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 7 of 50) Land No. Buffer Type Direction Table 8-1. Land Name (Sheet 8 of 50) Land Name Land No.
Processor Land Listing Table 8-1. Land Name (Sheet 9 of 50) Land Name Land No. Buffer Type Direction Table 8-1. Land Name (Sheet 10 of 50) Land Name Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 11 of 50) Land No. Buffer Type Direction Table 8-1. Land Name (Sheet 12 of 50) Land Name Land No.
Processor Land Listing Table 8-1. Land Name (Sheet 13 of 50) Land Name Land No. Buffer Type Direction DDR2_ECC[3] AB26 SSTL I/O DDR2_ECC[4] AB30 SSTL I/O DDR2_ECC[5] AD30 SSTL DDR2_ECC[6] W27 SSTL DDR2_ECC[7] AA27 SSTL DDR2_MA_PAR M18 SSTL DDR2_MA[00] AB18 DDR2_MA[01] R19 DDR2_MA[02] U19 DDR2_MA[03] T20 Table 8-1. Land Name (Sheet 14 of 50) Land Name Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 15 of 50) Table 8-1. Land Name (Sheet 16 of 50) Land No. Buffer Type Direction Land Name Land No.
Processor Land Listing Table 8-1. Land Name (Sheet 17 of 50) Land Name Land No. Buffer Type Direction Table 8-1. Land Name (Sheet 18 of 50) Land Name Land No. Buffer Type Direction DDR3_ECC[6] F26 SSTL I/O DMI_TX_DP[2] B44 PCIEX O DDR3_ECC[7] H26 SSTL I/O DMI_TX_DP[3] C45 PCIEX O DDR3_MA_PAR B18 SSTL O TXT_PLTEN DDR3_MA[00] A19 SSTL O DRAM_PWR_OK_C01 V52 CMOS I CW17 CMOS1.
Processor Land Listing Table 8-1. Land Name (Sheet 19 of 50) Land Name Land No. Buffer Type Direction Table 8-1. Land Name (Sheet 20 of 50) Land Name Land No.
Processor Land Listing Table 8-1. Land Name (Sheet 21 of 50) Land Name Land No. Buffer Type Table 8-1. Direction Land Name (Sheet 22 of 50) Land Name Land No.
Processor Land Listing Table 8-1. Land Name (Sheet 23 of 50) Land Name Land No. Buffer Type Direction QPI0_DRX_DN[18] BN49 QPI I QPI0_DRX_DN[19] BM48 QPI I QPI0_DRX_DP[00] BG51 QPI QPI0_DRX_DP[01] BF52 QPI QPI0_DRX_DP[02] BE53 QPI0_DRX_DP[03] BE55 QPI0_DRX_DP[04] QPI0_DRX_DP[05] Table 8-1. Land Name (Sheet 24 of 50) Land Name Land No.
Processor Land Listing Table 8-1. Land Name (Sheet 25 of 50) Land Name Land No. Buffer Type Direction Table 8-1. Land Name (Sheet 26 of 50) Land Name Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 27 of 50) Land No. Buffer Type Table 8-1. Direction Land Name (Sheet 28 of 50) Land Name Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 29 of 50) Table 8-1. Direction Land Name Land Name (Sheet 30 of 50) Land No. Buffer Type Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 31 of 50) Land No. Buffer Type VCC BE9 PWR VCC BF10 PWR VCC BF12 VCC BF14 VCC VCC Table 8-1. Direction Land Name Land Name (Sheet 32 of 50) Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 33 of 50) Land No. Buffer Type VCC BU7 PWR VCC BU9 PWR VCC BV10 VCC BV12 VCC VCC Table 8-1. Direction Land Name Land Name (Sheet 34 of 50) Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 35 of 50) Land No. Buffer Type VSA AH16 PWR VSA AH2 PWR VSA AH4 VSA AH6 VSA VSA Table 8-1. Direction Land Name Land Name (Sheet 36 of 50) Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 37 of 50) Land No. Buffer Type Table 8-1. Direction Land Name Land Name (Sheet 38 of 50) Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 39 of 50) Land No. Buffer Type Table 8-1. Direction Land Name Land Name (Sheet 40 of 50) Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 41 of 50) Land No. Buffer Type VSS CC29 GND VSS CC3 GND VSS CC43 VSS CC47 VSS VSS Table 8-1. Direction Land Name Land Name (Sheet 42 of 50) Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 43 of 50) Land No. Buffer Type Table 8-1. Direction Land Name Land Name (Sheet 44 of 50) Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 45 of 50) Land No. Buffer Type VSS DD36 GND VSS DD38 GND Table 8-1. Direction Land Name Land Name (Sheet 46 of 50) Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 47 of 50) Land No. Buffer Type Table 8-1. Direction Land Name (Sheet 48 of 50) Land Name Land No.
Processor Land Listing Table 8-1. Land Name (Sheet 49 of 50) Land Name Land No. Buffer Type VTTD AT42 PWR VTTD AY42 PWR VTTD BD42 VTTD BH42 VTTD BK56 VTTD BL51 VTTD VTTD Table 8-1. Direction Land Name (Sheet 50 of 50) Land Name Land No. Buffer Type VTTD BU47 PWR VTTD BV42 PWR PWR VTTD BY20 PWR PWR VTTD BY22 PWR PWR VTTD CA21 PWR PWR VTTD CA23 PWR BM42 PWR VTTD_SENSE BP42 BR55 PWR 8.2 Listing by Land Number Table 8-2.
Processor Land Listing Table 8-2. Land No. Land Number (Sheet 3 of 49) Table 8-2. Land Number (Sheet 4 of 49) Land Name Buffer Type Direction Land No.
Processor Land Listing Table 8-2. Land No. Land Number (Sheet 5 of 49) Land Name Buffer Type Direction Table 8-2. Land No.
Processor Land Listing Table 8-2. Land No. Land Number (Sheet 7 of 49) Land Name Buffer Type AH48 PE3C_RX_DN[8] PCIEX3 AH50 PE3C_RX_DN[10] PCIEX3 AH52 PE_RBIAS PCIEX3 AH54 PE2B_TX_DP[5] PCIEX3 AH56 PE2C_RX_DP[8] PCIEX3 AH58 VSS GND AH6 VSA AH8 VSA Direction Table 8-2. Land Number (Sheet 8 of 49) Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 9 of 49) Buffer Type Direction Table 8-2. Land No. Land Number (Sheet 10 of 49) Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 11 of 49) Table 8-2. Land Number (Sheet 12 of 49) Land No. Land Name Buffer Type Direction Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 13 of 49) Direction Table 8-2. Land No. Land Number (Sheet 14 of 49) Land No.
Processor Land Listing Table 8-2. Land No. Land Number (Sheet 15 of 49) Land Name Buffer Type Direction Table 8-2. Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 17 of 49) Land No. Land Name Buffer Type Direction Table 8-2. Land Number (Sheet 18 of 49) Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 19 of 49) Land No. Land Name Buffer Type BT6 VCC PWR BT8 VCC PWR Direction Table 8-2. Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 21 of 49) Land No. Land Name Buffer Type C15 VCCD_23 C17 VCCD_23 C19 VCCD_23 PWR C21 VCCD_23 PWR Land Number (Sheet 22 of 49) Land No. Land Name Buffer Type Direction PWR CA47 QPI0_DTX_DN[12] QPI O PWR CA49 QPI0_DTX_DN[13] QPI O CA5 VSS GND CA51 QPI0_DTX_DP[11] QPI CA53 VTTA PWR CA55 VSS GND C23 VCCD_23 PWR C25 DDR3_ECC[3] SSTL Direction Table 8-2.
Processor Land Listing Table 8-2. Land Number (Sheet 23 of 49) Land No. Land Name Buffer Type CC21 DDR0_PAR_ERR_N CC23 DDR0_CS_N[2] CC25 CC27 Table 8-2. Land Number (Sheet 24 of 49) Direction Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 25 of 49) Table 8-2. Land Number (Sheet 26 of 49) Land No. Land Name Buffer Type Direction Land No.
Processor Land Listing Table 8-2. Land No. Land Number (Sheet 27 of 49) Land Name Buffer Type Direction CJ31 DDR0_DQ[41] SSTL CJ33 DDR0_DQS_DP[05] SSTL CJ35 DDR0_DQ[43] CJ37 DDR0_DQ[60] CJ39 DDR0_DQS_DP[16] CJ41 DDR0_DQ[62] CJ43 VSS CJ45 VSS Table 8-2. Land Number (Sheet 28 of 49) Land No.
Processor Land Listing Table 8-2. Land No. Land Number (Sheet 29 of 49) Land Name Buffer Type Direction Table 8-2. Land No.
Processor Land Listing Table 8-2. Land No. Land Number (Sheet 31 of 49) Land Name Buffer Type Direction Table 8-2. Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 33 of 49) Land No. Land Name Buffer Type CV30 VSS CV32 VSS Land Number (Sheet 34 of 49) Land No. Land Name Buffer Type GND CW53 VSS GND GND CW55 VSS GND CV34 VSS GND CV36 DDR1_DQ[53] SSTL Direction Table 8-2.
Processor Land Listing Table 8-2. Land Number (Sheet 35 of 49) Table 8-2. Land Number (Sheet 36 of 49) Land No. Land Name Buffer Type Direction Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 37 of 49) Land No. Land Name Buffer Type DC33 DDR1_DQS_DP[14] DC35 DDR1_DQ[42] DC37 DDR1_DQ[61] DC39 DDR1_DQS_DP[07] DC41 VSS GND DC43 QPI1_DTX_DN[18] QPI O DC45 QPI1_DTX_DN[15] QPI O DC47 QPI1_DTX_DN[12] QPI O DC49 QPI1_DTX_DP[09] QPI O DC5 VSS GND Table 8-2. Land Number (Sheet 38 of 49) Direction Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 39 of 49) Land No. Land Name E17 E19 202 Table 8-2. Land Number (Sheet 40 of 49) Buffer Type Direction Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 41 of 49) Direction Table 8-2. Land No. Land Number (Sheet 42 of 49) Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 43 of 49) Table 8-2. Land Number (Sheet 44 of 49) Land No. Land Name Buffer Type Direction Land No. Land Name K6 DDR3_DQS_DP[06] SSTL I/O M30 DDR3_DQS_DN[12] SSTL I/O K8 VSS GND M32 DDR3_DQ[24] SSTL I/O 204 Buffer Type L1 DDR3_DQ[62] SSTL I/O M34 VSS GND L11 DDR3_DQS_DN[05] SSTL I/O M36 VSS GND Direction L13 DDR3_DQ[41] SSTL I/O M38 DDR3_DQS_DP[10] SSTL I/O L15 DRAM_PWR_OK_C23 CMOS1.
Processor Land Listing Table 8-2. Land Number (Sheet 45 of 49) Table 8-2. Land Number (Sheet 46 of 49) Land No. Land Name Buffer Type Direction Land No.
Processor Land Listing Table 8-2. Land No. 206 Land Number (Sheet 47 of 49) Land Name Table 8-2. Land Number (Sheet 48 of 49) Buffer Type Direction Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 49 of 49) Land No.
Processor Land Listing 208 Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 Product Families Datasheet Volume One of Two
Package Mechanical Specifications 9 Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array (FCLGA12) package that interfaces with the baseboard via an LGA2011-0 socket. The package consists of a processor mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.
Package Mechanical Specifications Table 9-1. Processor Package Sizes Notes1 Package Size and Processor TDP SKU Package A: MCC and LCC die size 52.5 mm x 45 mm (Figure 9-2 and Figure 9-3) 150W (8-core) 130W 1U (10/8-core) 130W 2U (8/6/4-core) 130W 1S WS (6/4-core) 2 115W (10-core) 95W (10/8/6/4-core) 80W (6/4-core) 70W (10-core) 60W (6-core) LV95W-10C LV70W-10C and LV70W-8C LV50W-6C Package B: HCC die size 52.
Package Mechanical Specifications Figure 9-2. Processor PMD Package A (52.
Package Mechanical Specifications Figure 9-3. 212 Processor PMD Package A (52.
Package Mechanical Specifications Figure 9-4. Processor PMD Package B (52.
Package Mechanical Specifications Figure 9-5. 214 Processor PMD Package B (52.
Package Mechanical Specifications 9.3 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keep-out zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Do not contact the Test Pad Area with conductive material. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 9-3 through Figure 9-4 for keep-out zones.
Package Mechanical Specifications 9.7 Processor Mass Specification The typical mass of the processor is currently 45 grams. This mass [weight] includes all the components that are included in the package. 9.8 Processor Materials Table 9-4 lists some of the package components and associated materials. Table 9-4. Processor Materials Component Material Integrated Heat Spreader (IHS) Nickel Plated Copper Substrate Halogen Free, Fiber Reinforced Resin Substrate Lands 9.
Boxed Processor Specifications 10 Boxed Processor Specifications 10.1 Introduction Intel boxed processors are intended for system integrators who build systems from components available through distribution channels. The Intel® Xeon® processor E52600 v2 product family (LGA2011-0) processors will be offered as Intel boxed processors, however the thermal solutions will be sold separately. Boxed processors will not include a thermal solution in the box.
Boxed Processor Specifications Figure 10-1. STS200C Passive/Active Combination Heat Sink (with Removable Fan) Figure 10-2. STS200C Passive/Active Combination Heat Sink (with Fan Removed) The STS200C utilizes a fan capable of 4-pin pulse width modulated (PWM) control. Use of a 4-pin PWM controlled active thermal solution helps customers meet acoustic targets in pedestal platforms through the baseboard’s ability to directly control the RPM of the processor heat sink fan. See Section 10.
Boxed Processor Specifications sink solutions. The retention solution used for the STS200P Heat Sink Solution is called the ILM Retention System (ILM-RS).The retention solution used for the STS200PNRW Narrow Heat Sink Solution is called the Narrow ILM Retention System (Narrow ILM-RS). Figure 10-3. STS200P and STS200PNRW 25.5 mm Tall Passive Heat Sinks 10.2 Mechanical Specifications This section documents the mechanical specifications of the boxed processor solution. 10.2.
A B C D 8 7 6 8 7 BALL 1 CORNER POSITIONAL MARKING (FOR REFERENCE ONLY) 93.0 MAX THERMAL SOLUTION ENVELOPE AND MECHANICAL PART CLEARANCE 2X FINGER ACCESS 8 6 (51.0 ) SOCKET BODY OUTLINE (FOR REFERENCE ONLY) 2X 46.0 SOCKET ILM HOLE PATTERN 93.0 MAX THERMAL SOLUTION ENVELOPE AND MECHANICAL PART CLEARANCE (FINGER ACCESS NOT INCLUDED) THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION.
Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 Product Families Datasheet Volume One of Two A B C D 8 7 6 8 (93.0 ) A 2X 7.05 SEE DETAIL 2X 8.80 7 (93.0 ) 12.80 6 AS VIEWED FROM PRIMARY SIDE OF MAINBOARD 2X 3.45 2X 41.46 2X 53.808 2X 92.0 18.20 2X 31.55 2X 3.30 2X 4.50 5 5 SEE DETAIL 2X 25.25 THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION.
A B C D 8 7 6 8 7 2X 5.0 4X R7.0 22.37 4.8 4X NO ROUTE ZONE THRU ALL LAYERS 6 5 R1.00 TYP 5 AS VIEWED FROM SECONDARY SIDE OF MAINBOARD 2X 23.40 14.0 71.5 THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION. IT IS DISCLOSED IN CONFIDENCE AND ITS CONTENTS MAY NOT BE DISCLOSED, REPRODUCED, DISPLAYED OR MODIFIED, WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION. 4 4 2X 26.50 81.5 3 PTMI DEPARTMENT 3 R G11950 SHT. 3 REV B 2200 MISSION COLLEGE BLVD. P.O.
8 7 6 76.50 R 2200 MISSION COLLEGE BLVD. P.O. BOX 58119 SANTA CLARA, CA 95052-8119 DWG. NO 2 D SHT. 4 REV SIZE DRAWING NUMBER G11950 G11950 B 1 Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 Product Families Datasheet Volume One of Two A B 8 7 TOP SURFACE OF MOTHERBOARD 81.50 4.38 PRIMARY SIDE 3D HEIGHT RESTRICTION ZONES AND VOLUMETRIC SWEEPS OF LOADPLATE AND LEVER OPENING/CLOSING 6 97.0° MIN 93.00 97.0° MIN .03 4 93.
A B C D 8 7 6 5 8 [ B 0 -0.25 +0.000 3.602 -0.009 91.50 C ] 7 +1.00 0 +0.039 -0.000 TOP VIEW ] 0.472 0 -0.25 +0.000 -0.009 3.602 91.50 [ [ 4X 12.00 ] 6 A +1.00 0 +0.039 -0.000 0.472 ] 64.00 [2.520] MAX. AIRFLOW DIRECTION [ 4X 12.00 5 THIS DRAWING CONTAINS INTEL CORPORAT ION CONFIDENTIAL INFORMATION. IT IS DISCLOSED IN CONFIDENCE AND ITS CONT ENTS MAY NOT BE DISCLOSED, REPRODUCED, DI SPLAYED OR MODIFIED, WITHOUT THE PRI OR WRITTEN CONSENT OF INTEL CORPORAT ION.
Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 Product Families Datasheet Volume One of Two A B C D 8 7 6 5 8 80.00 [3.150] 9 38.00 #0.50 [1.496 #0.019 ] A 7 A-A 9 80.00 [3.150] 38.00 #0.50 [1.496 #0.019 ] SECTION 6 BOTTOM VIEW FLATNESS ZONE, SEE NOTE 7 0.077 [0.0030] B SEE DETAIL 5 AIRFLOW DIRECTION A C SEE DETAIL AIRFLOW DIRECTION TOP VIEW THIS DRAWING CONTAINS INTEL CORPORAT ION CONFIDENTIAL INFORMATION.
Boxed Processor Specifications Figure 10-10.
Boxed Processor Specifications Figure 10-11.
Boxed Processor Specifications 10.2.2 Boxed Processor Retention Mechanism and Heat Sink Support (ILM-RS) Baseboards designed for use by a system integrator should include holes that are in proper alignment with each other to support the boxed processor. The standard and narrow ILM-RSs are designed to extend air-cooling capability through the use of larger heat sinks with minimal airflow blockage and bypass. ILM-RS retention transfers load to the baseboard via the ILM Assembly.
Boxed Processor Specifications Figure 10-12.Fan Cable Connector Pin Out For 4-Pin Active Thermal Solution Table 10-3. PWM Fan Connector Pin and Wire Description 10.3.1 Pin Number Signal Wire Color 1 Ground Black 2 Power (+12V) Yellow 3 Sense: 2 pulse per revolution Green 4 Control: 21KHz - 28KHz Blue Boxed Processor Cooling Requirements As previously stated the boxed processor will have three thermal solutions available. Each configuration will require unique design considerations.
Boxed Processor Specifications 10.3.1.2 STS200P and STS200PNRW (25.5mm Tall Passive Heat Sink Solution) (Blade + 1U + 2U Rack) These passive solutions are intended for use in SSI Blade, 1U or 2U rack configurations. It is assumed that a chassis duct will be implemented in all configurations. For a list processor and thermal solution boundary conditions, such as Psica, TLA, airflow, flow impedance, and so forth, see Table 10-4.
Boxed Processor Specifications Table 10-4. Server Thermal Solution Boundary Conditions (Sheet 2 of 2) TDP Thermal Solution ΨCA2 (˚C/W) TLA 1 (˚C) Airflow 3 (CFM) Delta P (inch of H2O) Heatsink Volumetric4 (mm) 95W - 10/8 Core STS200C (with fan) 0.201 55.9 Max RPM NA 91.5x91.5x64 95W - 10/8 Core STS200P 0.263 50.0 16 0.406 91.5x91.5x25.5 95W - 10/8 Core STS200PNRW 0.274 49.0 14 0.347 70x106x25.5 95W - 10/8 Core STS200C (without fan) 0.201 55.9 26 0.14 91.5x91.
Boxed Processor Specifications 10.4 Boxed Processor Contents The Boxed Processor and Boxed Thermal Solution contents are outlined below.
