Mobile 3rd Generation Intel Core Family Specification Sheet

48 Specification Update
BU97. VM Exits Due to GETSEC May Save an Incorrect Value for “Blocking by STI” in the
Context of Probe-Mode Redirection
Problem: The GETSEC instruction causes a VM exit when executed in VMX non-root
operation. Such a VM exit should set bit 0 in the Interruptability-state field in the
virtual-machine control structure (VMCS) if the STI instruction was blocking interrupts
at the time GETSEC commenced execution.
Due to this erratum, a VM exit executed in
VMX non-root operation may erroneously clear bit 0 if redirection to probe mode occurs
on the GETSEC instruction.
Implication: After returning from probe mode, a virtual interrupt may be incorrectly delivered prior
to GETSEC instruction. Intel has not observed this erratum with any commercially
software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
BU98. Specific Graphics Blitter Instructions May Result in Unpredictable Graphics
Controller Behavior
Problem: Specific source-copy blitter instructions in Intel
®
HD Graphics 2500 and 4000 Processor
may result in unpredictable behavior when a blit source and destination overlap.
Implication: Due to this erratum, the processor may exhibit unpredictable graphics controller
behavior. Intel has not observed this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
BU99. IA32_MC5_CTL2 is Not Cleared by a Warm Reset
Problem: IA32_MC5_CTL2 MSR (285H) is documented to be cleared on any reset. Due to this
erratum this MSR is only cleared upon a cold reset.
Implication: The algorithm documented in Software Developer's Manual, Volume 3, section titled
"CMCI Initialization” or any other algorithm that counts the IA32_MC5_CTL2 MSR being
cleared on reset will not function as expected after a warm reset.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
BU100. CPUID Instruction May Not Report the Processor Number in the Brand
String for Intel
®
Core™ i3-3227U and i5-3337U Processors.
Problem: When the CPUID instruction is executed with EAX = 80000002H, 80000003H, and
80000004H, the returned brand string may be incomplete; it may be missing the
processor number.
Implication: When this erratum occurs, the processor may be missing the processor number in the
brand string. In addition, if the affected processors are paired with the Intel
®
7 Series
Chipset BD82UM77 chipset, the BIOS may incorrectly report this combination as
unsupported.
Workaround: It is possible for the BIOS to contain a workaround for this erratum, except if paired
with the Intel 7 Series Chipset BD82UM77 chipset.
Status: For the steppings affected, see the Summary Tables of Changes.
BU101. Performance Monitor Counters May Produce Incorrect Results
Problem: When operating with SMT enabled, a memory at-retirement performance monitoring
event (from the list below) may be dropped or may increment an enabled event on the