Desktop 4th Generation Specification Sheet
Table Of Contents
- Contents
- Revision History
- 1.0 Introduction
- 2.0 Interfaces
- 3.0 Technologies
- 3.1 Intel® Virtualization Technology (Intel® VT)
- 3.2 Intel® Trusted Execution Technology (Intel® TXT)
- 3.3 Intel® Hyper-Threading Technology (Intel® HT Technology)
- 3.4 Intel® Turbo Boost Technology 2.0
- 3.5 Intel® Advanced Vector Extensions 2.0 (Intel® AVX2)
- 3.6 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)
- 3.7 Intel® Transactional Synchronization Extensions - New Instructions (Intel® TSX-NI)
- 3.8 Intel® 64 Architecture x2APIC
- 3.9 Power Aware Interrupt Routing (PAIR)
- 3.10 Execute Disable Bit
- 3.11 Supervisor Mode Execution Protection (SMEP)
- 4.0 Power Management
- 4.1 Advanced Configuration and Power Interface (ACPI) States Supported
- 4.2 Processor Core Power Management
- 4.3 Integrated Memory Controller (IMC) Power Management
- 4.4 PCI Express* Power Management
- 4.5 Direct Media Interface (DMI) Power Management
- 4.6 Graphics Power Management
- 5.0 Thermal Management
- 5.1 Desktop Processor Thermal Profiles
- 5.2 Thermal Metrology
- 5.3 Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 1.1
- 5.4 Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 2.0
- 5.5 Processor Temperature
- 5.6 Adaptive Thermal Monitor
- 5.7 THERMTRIP# Signal
- 5.8 Digital Thermal Sensor
- 5.9 Intel® Turbo Boost Technology Thermal Considerations
- 6.0 Signal Description
- 6.1 System Memory Interface Signals
- 6.2 Memory Reference and Compensation Signals
- 6.3 Reset and Miscellaneous Signals
- 6.4 PCI Express*-Based Interface Signals
- 6.5 Display Interface Signals
- 6.6 Direct Media Interface (DMI)
- 6.7 Phase Locked Loop (PLL) Signals
- 6.8 Testability Signals
- 6.9 Error and Thermal Protection Signals
- 6.10 Power Sequencing Signals
- 6.11 Processor Power Signals
- 6.12 Sense Signals
- 6.13 Ground and Non-Critical to Function (NCTF) Signals
- 6.14 Processor Internal Pull-Up / Pull-Down Terminations
- 7.0 Electrical Specifications
- 8.0 Package Mechanical Specifications
- 9.0 Processor Ball and Signal Information

Contents
Revision History..................................................................................................................9
1.0 Introduction................................................................................................................10
1.1 Supported Technologies.........................................................................................11
1.2 Interfaces............................................................................................................ 12
1.3 Power Management Support...................................................................................12
1.4 Thermal Management Support................................................................................13
1.5 Package Support...................................................................................................13
1.6 Terminology.........................................................................................................13
1.7 Related Documents............................................................................................... 16
2.0 Interfaces................................................................................................................... 18
2.1 System Memory Interface...................................................................................... 18
2.1.1 System Memory Technology Supported.......................................................19
2.1.2 System Memory Timing Support................................................................. 20
2.1.3 System Memory Organization Modes........................................................... 21
2.2 PCI Express* Interface.......................................................................................... 23
2.2.1 PCI Express* Support................................................................................23
2.2.2 PCI Express* Architecture.......................................................................... 24
2.2.3 PCI Express* Configuration Mechanism........................................................ 24
2.3 Direct Media Interface (DMI).................................................................................. 26
2.4 Processor Graphics................................................................................................28
2.5 Processor Graphics Controller (GT)..........................................................................28
2.5.1 3D and Video Engines for Graphics Processing.............................................. 29
2.5.2 Multi Graphics Controllers Multi-Monitor Support........................................... 31
2.6 Digital Display Interface (DDI)................................................................................31
2.7 Intel
®
Flexible Display Interface (Intel
®
FDI)............................................................37
2.8 Platform Environmental Control Interface (PECI)....................................................... 37
2.8.1 PECI Bus Architecture................................................................................37
3.0 Technologies...............................................................................................................39
3.1 Intel
®
Virtualization Technology (Intel
®
VT)............................................................. 39
3.2 Intel
®
Trusted Execution Technology (Intel
®
TXT).....................................................43
3.3 Intel
®
Hyper-Threading Technology (Intel
®
HT Technology)....................................... 44
3.4 Intel
®
Turbo Boost Technology 2.0..........................................................................45
3.5 Intel
®
Advanced Vector Extensions 2.0 (Intel
®
AVX2)................................................45
3.6 Intel
®
Advanced Encryption Standard New Instructions (Intel
®
AES-NI).......................46
3.7 Intel
®
Transactional Synchronization Extensions - New Instructions (Intel
®
TSX-NI)..... 46
3.8 Intel
®
64 Architecture x2APIC................................................................................ 47
3.9 Power Aware Interrupt Routing (PAIR)....................................................................48
3.10 Execute Disable Bit..............................................................................................48
3.11 Supervisor Mode Execution Protection (SMEP)........................................................48
4.0 Power Management.................................................................................................... 49
4.1 Advanced Configuration and Power Interface (ACPI) States Supported......................... 50
4.2 Processor Core Power Management......................................................................... 51
4.2.1 Enhanced Intel
®
SpeedStep
®
Technology Key Features..................................51
4.2.2 Low-Power Idle States............................................................................... 52
Contents—Processor
Desktop 4th Generation Intel
®
Core
™
Processor Family, Desktop Intel
®
Pentium
®
Processor Family, and Desktop Intel
®
Celeron
®
Processor Family
December 2013 Datasheet – Volume 1 of 2
Order No.: 328897-004 3