. inter MCS® -80/85 FAMILY USER'S MANUAL Jan uary 1983 .
Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein.
Table of Contents CHAPTER 1 Part 1: Introduction to the Functions of a Computer ................................... 1-1 Part 2. Introduction to MCS®-85 ..................................................... 1-6 CHAPTER 2 Functional Description .............................................................. 2-1 CHAPTER 3 System Operation and Interfacing .................................................... 3-1 CHAPTER 4 The 8080 Central Processor Unit .....................................................
Introduction
CHAPTER 1 PART 1: INTRODUCTION TO THE FUNCTIONS OF A COMPUTER This chapter introduces certain basic computer concepts. It provides background information and definitions which will be useful in later chapters of this manual. Those already familiar with computers may skip this material, at their option. peripheral storage device, such as a floppy disk unit, or the output may constitute process control signals that direct the operations of another system, such as an automated assembly line.
registers eliminates the need to "shuffle" intermediate results back and forth between memory and the accumulator, thus improving processing speed and efficiency. cessor loads the address specified in the Call into its Program Counter. The next instruction fetched will therefore be the first step of the subroutine. The last instruction in any subroutine is a Return. Such an instruction need specify no address.
performs the arithmetic and logical operations on the binary data. Code or Operation Code. An eight-bit word used as an instruction code can distinguish between 256 alternative actions, more than adequate for most processors. The ALU must contain an Adder which is capable of combining the contents of two registers in accordance with the logic of binary arithmetic. This provision permits the processor to perform arithmetic manipulations on the data it obtains from memory and from its other inputs.
with a clearly defined activity IS called a State. And the interval between pulses of the timing oscillator is referred to as a Clock Period. As a general rule, one or more clock periods are necessary for the completion of a state, and there are several states in a cycle. had time to respond, it frees the processor's READY line, and the instruction cycle proceeds.
from memory to output devices goes by way of the processor. having the device accomplish the transfer directly. The pro· cessor must temporarily suspend its operation during such a transfer, to prevent conflicts that would arise if processor and peripheral device attempted to access memory simul· taneously. It is for this reason that a hold provision is in· cluded on some processors.
PART 2: INTRODUCTION TO MCS-85™ THE MCS·SS™ MICROCOMPUTER SYSTEM The basic philosophy behind the MCS·85 microcomputer system is one of logical, evolutionary advance in technology without the waste of discarding existing investments in hardware and software. The MCS-85 provides the existing 8080 user with an increase in performance, a decrease in the component count, operation from a single 5-Volt power supply, and still preserves 100% of his existing software investment.
INTRODUCTION TO MCS-85™ purpose organization and instruction set matched the requirements of these products. Recognizing that hardware was but a small part in the overall system picture, Intel developed both hardware and software tools for the design engineer so that the transition from prototype to production would be as simple and fast as possible.
INTRODUCTION TO MCS-85™ For the new microcomputer user, the software compatibility between the 8085A and the 8080A means that all of the software development tools that are available for the 8080A and all software libraries for 8080A will operate with the new design and thus save immeasurable cost in development and debug. SOFTWARE COMPATIBILITY As with any computer system the cost of software development far outweighs that of hardware.
MCS·S5™ SPECIAL PERIPHERAL ClK COMPONENTS READY The MCS-85 was designed to minimize the amount of components required for most systems. Intel designed several new peripheral components that combine memory, 110 and timer functions to fulfill this requirement. These new peripheral devices directly interface to the multiplexed MCS-85 bus structure and provide new levels in system integration for today's designer.
SERIAL DATA LINES INTERRUPTS I 11 RST 7.5 RST6.5 ! RST 5.5 r TRAP PORT A ~ '! r SIO PORT C I ! RESET IN SOO tt I I I J Il SI SO PORT B PCO- - - - - --PCs PAO- - - - ----PAl I I 1 POo- - - :...
INTERFACING TO MCS·80/8S™ PROGRAMMABLE PERIPHERAL COMPONENTS BOB5A The MCS·85 shares with the MCS-80 a wide range of peripheral components that solve system problems and provide the designer with a great deal of flexibility in his I/O, Interrupt and DMA structures. The MCS-85 is directly com· patible with these peripherals, and, with the ex· ception of the 8257-5 DMA controller, needs no additional circuitry for their interface in a minimum system.
INTERFACING TO STANDARD MEMORY The MC5-85 was designed to support the full range of system configurations from small 3 chip applications to large memory and 110 applications. The 8085A CPU issues advanced READIWRITE status signals (SO, 51, and 101M) so that, in the case of large systems, these signals could be used to simplify bus arbitration logic and dynamic RAM refresh circuitry.
INTRODUCTION TO MCS-85™ SYSTEM PERFORMANCE 20 15 The true benchmark of any microcomputerbased system is the amount of tasks that can be performed by the system in a given period of time. Increasing speed of CPU instruction execution has been the common approach to increasing system throughput but this puts a greater strain on the memory access requirement and bus operation than is usually practical for most applications.
Functional Description 2
CHAPTER 2 SOSSA FUNCTIONAL DESCRIPTION 2.1 WHAT TH E 808SA IS The 8085A is an 8-bit general-purpose microprocessor that is very cost-effective in small systems because of its extraordinarily low hardware overhead requirements. At the same time it is capable of accessing up to 64K bytes of memory and has status lines for controlling large systems. functions to perform READ and WRITE operations and also to select memory or 1/0 ports. The 8085A can address up to 256 different 1/0 locations.
The 8085A's CPU registers are distinguished as follows: • The accumulator (ACC or A Register) is the focus of all of the accumulator instructions (Table 4-1), which include arithmetic, logic, load and store, and I/O instructions. It is an 8-bit register only, (However, see Flags, in this list.) • The program counter (PC) always points to the memory location of the next instruction to be executed. It always contains a 16-bit address.
FUNCTIONAL DESCRIPTION 2.2.4 Arlthmetlc·Loglc Unit (ALU) The AlU contains the accumulator and the flag register (described in Sections 2.2.1- and 2.2.2) and some temporary registers that are inaccessible to the programmer. Arithmetic, logic, and rotate operations are performed by the AlU. The results of these operations can be deposited in the accumulator, or they can be transferred to the internal data bus for use elsewhere.
Iii,'I. FUNCTIONAL DESCRIPTION RST 5.5, 6.5, and 7.5 are also subject to being enabled or disabled by the EI and 01 instructions, respectively. INTR, RST 5.5, and RST 6.5 are level-sensitive, meaning that these inputs may be acknowledged by the processor when they are held at a high level. RST 7.5 is edgesensitive, meaning that an internal flip-flop in the BOB5A registers the occurrence of an interrupt the instant a rising edge appears on the RST 7.5 input line.
FUNCTIONAL DESCRIPTION • The 8085A, before respondin~ to the RST 7.5 interrupt, receives a RES T IN signal from an external source; this also activates the internal reset. terrupt mask) and SIM (set interrupt mask) instruction listings. Interrupt functions and their priorities are shown in the table that follows. • The 8085A executes a SIM instruction, with accumulator bit 4 previously set to 1. (See Figure 2-4.) Name The third type of hardware interrupt is TRAP.
FUNCTIONAL DESCRIPTION 2.3 HOW THE MCS·85 SYSTEM WORKS components with improved timing margins and access requirements. (See Figure 2-8.) To enhance the system integration of MCS-85, several special components with combined memory and I/O were designed. These new devices directly interface to the multiplexed bus of the 8085A. The pin locations of the 8085A and the special peripheral components are assigned to minimize PC board area and to allow for efficient layout.
FUNCTIONAL DESCRIPTION 2.3.1 Multiplexed Bus Cycle Timing The execution of any 8085A program consists of a sequence of READ and WRITE operations, of which each transfers a byte of data between the 8085A and a particular memory or 1/0 address. These READ and WRITE operations are the only communication between the processor and the other components, and are all that is necessary to execute any instruction or program.
FUNCTIONAL DESCRIPTION MACHINE CYCLE OPCODE FETCH MEMORY READ MEMORY WRITE 1/0 READ 110 WRITE INTR ACKNOWLEDGE BUS IDLE O=Logic"O" (OF) (MR) (MW) (lOR) (lOW) (INA) (81l: DAD INA(RST/TRAP) HALT STATUS 101M S1 so 1 1 0 1 0 1 1 1 0 1 0 1 0 1 1 0 1 0 0 0 0 1 1 1 0 1 TS CONTROL RD WR INTA 0 0 1 0 1 1 1 1 TS 1 1 0 1 0 1 1 1. TS 1 1 1 1 1 0 1 1 1 1=Logic"1" TS=High Impedance X=Unspecified FIGURE 2·10 808SA MACHINE CYCLE CHART machine cycle.
FUNCTIONAL DESCRIPTION The SOS5A also sends out a 16-bit address at the beginning of every machine cycle to identify the particular memory location or I/O port that the machine cycle applies to. In the case of an OF cycle, the contents of the program counter is placed on the address bus. The high order byte (PCH) is placed on the A8~A15Iines, where it will stay until at least T4. The low order byte (PCl) is placed on the ADo-AD7 lines, whose three-state drivers are enabled if not found already on.
FUNCTIONAL DESCRIPTION SIGNAL eLK 101M, S1,SO ALE FIGURE 2·13 OPCODE FETCH MACHINE CYCLE (OF DCX INSTRUCTION) During T5 and T6, of DCX, the CPU will decrement the designated register. Since the As-A15 lines are driven by the address latch circuits, which are part of the incrementerldecrementer logic, the Aa-A15 lines may change during T5 and T6. Because the value of As-A15 can vary during T4-T6, it is most important that all memory and 1/0 devices on...!De system bus qua~ their selection with RD.
FUNCTIONAL DESCRIPTION M1 (OF) SIGNAL ClK T1 T2 T3 TWAIT T4 TS TS - L IL IL IL IL . IL..ILJ tx tx );- ----~< tx j ! 101M, I-- S1,SO I-- IO/M-0,S1-1,SO-1 I-AS-A16 PCH UNSPECIFIED I-- OUT I-AD O·AD7 IN PCl ~--- DO.[)7 (DCX) I-- ALE I-- v---\ ~--- J 1 '~ iffi READY ...... "'C..--- ~ ,.... "C--- ~ FIGURE 2·14 OPCODE FETCH MACHINE CYCLE WITH ONE WAIT STATE MR OR lOR MR OR lOR SIGNAL T1 C~K 101M, S1,SO AS"A1S AOo·AD7 ....
FUNCTIONAL DESCRIPTION The memory address used in the OF cycle is always the contents of the program counter, which pOints to the current instruction, while the address used in the MR cycle can have several possible origins. Also, the data read in during an MR cycle is placed in the appropriate register, not the instruction register. 2.3.
FUNCTIONAL DESCRIPTION ~f WR. The ADo-AD7 lines are guaranteed to be stable both before and after the rising edge of WR. 1/0 WRITE (lOW): As Figure 2-16 shows, the timing for an 1/0 WRITE (lOW) machine cycle is the same as an MW machine cycle except that 101M = 0 during the MW cycle and 101M = during the lOW cycle. As with the lOR cycle discussed previously, the address used in an lOW cycle is the 1/0 port number which is duplicated on both the high and low bytes of the address bus.
FUNCTIONAL DESCRIPTION logical choices, since they both force the processor to push the contents of the program counter onto the stack before jumping to a new location. In Figure 2-17 it is assumed that a CALL opcode is sent to the CPU during M 1• The CALL opcode could have been placed there bya device like the 8259 programmable interrupt controller. Now that the CPU has accessed the entire instruction used to acknowledge the interrupt, it will execute that instruction ..
FUNCTIONAL DESCRIPTION 2.3.5 The other time when the BUS IDLE machine cycle occurs is during the internal opcode generation for the RST or TRAP interrupts. Figure 2-19 illustrates the BI cycle generated in response to RST 7.5. Since this interrupt is rising-edgetriggered, it sets an internal latch; that latch is sampled at the falling edge of the next to the last T-state of the previous instruction.
FUNCTIONAL DESCRIPTION In Figure 2-20 the RST 7.5 line is pulsed during THALT. Since RST 7.5 is a rising-edge-triggered interrupt, it will set an internal latch which is sampled during CLK = "1" of every THALT state (as well as during CLK = "1" two T states before any M1 • T1') The fact that the latched interrupt was high (assuming that INTE FF = 1 and the RST 7.5 mask = 0) will force the CPU to exit the THALT state at the end of the next CLK period, and to enter M1 • T1.
FUNCTIONAL DESCRIPTION The 8085A accepts the first unmasked, enabled interrupt sampled; thereafter, all interrupt sampling is inhibited. The interrupt thus accepted will inevitably be executed when the CPU exits the HOLD state, even at the expense of holding off higher-priority interrupts (including TRAP). (See Figure 2-22.) 2.3.6 HOLD and HALT States The 8085A uses the THOLD state to momentarily cease executing machine cycles, allowing external devices to gain control of the bus and peform DMA cycles.
FUNCTIONAL DESCRIPTION SIGNALS CLK THALT ~ THALl THAll ~ ~ THOLD ~ Tl THOLD ~ ~ J ALE I HOLD IJ \ -r""' I HLDA L-=-' LOW PRIORI". INTERRUPT CYCLE EXITS HALT IMMEDIATELY AFTER HOLD REMOVED INTERRUPT ACCEPTED HERE CAUSES SAMPLING TO BE INHIBITED - - INHIBITING HIGHER INTERRUPTS (EVEN TRAP) LOW PRIORITY INTERRUPT(S) I \ V HIGH PRIORITY INTERRUPT(S) 'I FIGURE 2-22 SOSSA HOLD VS INTERRUPTS - 2_3.7 HALT MODE Power On and RESET IN CPU will enter M1 • T1 for the next T state.
FUNCTIONAL DESCRIPTION M,(OF) POWER SUPPLY TRESET +5V .~ Vee .7J==-> T, T, 4.7SV 10ms.c - OV Vaa (INTERNAL) -2V.1- ,,-~ 2.4V . . . RESET IN OV. .. _---- .......... ,,-"- ~ ,,-"- FIGURE 2·23 POWER·ON TIMING Following RESET, the SOS5A will start executing instructions at location 0 with the interrupt system disabled, as shown in Figure 2-24. SIGNAL ClK Figure 2-24 also shows READ and WRITE operations being terminated by a RESET signal.
FUNCTIONAL DESCRIPTION M1 (OF) M1 (OF) M1 (OF) SIGNAL T1 T2 T3 V V
FUNCTIONAL DESCRIPTION MCS·85™ System Bus The MCS-85 bus is terminated on one end by the 8085A and the other end by various memory and 1/0 devices. The MCS-85 bus may be optionally de-multiplexed with an 8212 eight bit latch to provide an MCS-80 type bus. The following figure shows the major signals of the MCS-85 bus. MCS·80™ System Bus The MCS-80 bus is terminated on one end by the CPU-GROUP (consisting of the 8080A, 8224, 8228) and on the other end by the various memory and 1/0 circuits.
FUNCTIONAL DESCRIPTION MCS·85™ System Bus for READ CYCLE The basic timing of the MCS-85 BUS for a READ CYCLE is as follows: MCS·80™ System Bus for READ CYCLE The basic timing of the MCS-80 BUS for a READ CYCLE is as follows: Aa-AI5' IC?/M Ao-A7 ==><__________>C (OPTIONALLY=>( )( LATCHED SIGNALS) -'---_ _ _ _ _--< ALE Ri5 or INTA The MCS-80 first presents the address CD and shortly thereafter the control signal ®.
FUNCTIONAL DESCRIPTION The following observations of the two buses can be made: 1. The access times from address leaving the processor to returning data are almost identical, even though the SOS5A is operating 50% faster than the SOSO. 2. With the addition of an S212 latch to the SOS5A, the basic timings of the two systems are very similar. 3. The SOS5A has more time for address setup to FfO than the SOSO. 4. The MCS-SO has a wider RD signal, but a narrower WR signal than the SOS5A. 5.
System Operating and Interfacing 3
CHAPTER 3 SOSSA SYSTEM OPERATION AND INTERFACING 3.1 INTERFACING TO THE 8085A The 8085A interfaces to both memory and 1/0 devices by means of READ and WRITE machine cycles, the timing of which are identical. During each machine cycle the 8085A issues an address and a control signal, then either sends data out on the bus or reads data from the bus. The 8085A may be performing a READ machine cycle, but what it reads could be a ROM, RAM, I/O device, periph· eral device, or nothing.
SYSTEM OPERATION 3.3 ADDRESS ASSIGNMENT 3.3.2 Linear Selection Using an address bit as a chip select is referred to as linear selection. The direct consequence of linear selection is that you cut the available address space in half for each single address bit used as a chip enable. If this penalty is too high, you can always use an 8205 one-of-eight decoder. Also, some chips have multiple chip enables, which allows for some automatic decoding of the address. (See Figures 3-1 Band 3-1C.
SYSTEM OPERATION FIGURE 3-1A SINGLE CHIP A" _ _ _ _ _ _ _----1 8355/8755A ~ vee----~CE 10/~-------__I10/M MEMORY ADDRESS IX X X X I 0 1- - -I - 1/0 PORT { FIGURE 3-1 B MULTIPLECHIPS A,o- IX X X X l o x A, Aol 8156 CE 101M A13 101M MEMORY ADDRESS 8355/8755A rX 'I X X x> I"· . .
SYSTEM OPERATION memory portions of the 8x55 components share chip enables, so they are forced to live with each other's constraints. Third, only one 8205 is required per eight chips for the decoding; that's an overhead of only 1/8 of a chip per part. Figure 3.1 D shows a remedy to the problem illustrated in Figure 3.1 C, namely that I/O and memory portions of the chip are forced to live with each other's chip enable constraints.
SYSTEM OPERATION the MCS-80 peripherals require nonmultiplexed address lines, linear select is not too useful unless the address lines are latched. This is because connecting both the chip selects and the address lines of the MCS-80 peripherals to As-A15 would deplete all the useful addresses very quickly. replication of bits Ao-A7). Assuming that memory-mapped 1/0 is used, the addresses are shown in the boxes to the right in Figure 3-2.
SYSTEM OPERATION 11 I: FIGURE 3·3A DECODED CHIP SELECTS I A. I A. 8205 A,. A, A'3 A, 0, r A,s I O. 03 101M J~ I Ao A'2 F>---r E3 0, E, 0, E , 00 I les lA, Ao I :> 8259-5 .8255A-5 82535 1/0 PORT yes A, Ao I ~ 10 es WR I. ADo-AD, 0 1 r-- -Ao .A 0 OIX X X Aol 1/0 PORT 8251A RD 1 0 1 OIX X A, Aol 1/0 PORT - 10 0 11 X X A, Aol 0 1/0 PORT .
SYSTEM OPERATION have constructed a microcomputer system that has the following functions: PARTS FUNCTIONS 1 8085A 1 CPU (Clock cycle 1 8355/8755A :s 320 ns) 1 8156 2048 Bytes of either EPROM or ROM 1 Crystal 256 Bytes of RAM 4 Resistors 38110 Lines 1 Capacitor 5 Interrupts 1 Diode 1 + 5 Power Supply 1 Programmable Timerl Counter 1 Crystal and Oscillator 1 Clock 1 Power-on Reset By looking at the printed circuit layout of Figure 3.
SYSTEM OPERATION !!11 t 1 t t t 1 11 GND - '" :x 0 ...J --- o 0 .. en en ...J 0 :x o 5l 0 iii It> ~ l- ~ en <.D I- en en " "" I- "« ~~ 0 I- " Xl ~ 0 0 w ...J « '" iI- I:E I~ I~ § ¢ (8) I () w en W " .r00 « (3) ~ ...J u > 0 « N W M - X2 I.t) f ~-::- ~ ~ 1! lh ( z: o· .... ) : ~ :;( :;( :;( :;( :;( " ......L... iN I- 8085A 0 MANUAL RESET RESeT :;) Q ..
SYSTEM OPERATION •• -------- •• - -- L COMPON ENT SI DE SCALE: "='1:1 ••••••••••• I i······· ..·· ............
SYSTEM OPERATION VCC l! rr GND VCC -- 0 0 -1... ~ iN ~ :::l I"- 0 MANUAL RESET RESET N M
SYSTEM OPERATION 3.9 EXPANDED MCS·85™ SYSTEM Figure 3.8 shows the circuit Figure 3.6 ex· panded to its maximum size without the use of any extra logic. In an extremely small board area we can fit: PARTS FUNCTION 1 CPU (Clock cycle 18085A ~ 320ns) .
Functional Description 4
CHAPTER 4 THE 8080 CENTRAL PROCESSOR UNIT The 8080 is a complete 8-bit parallel, central processor unit (CPU) for use in general purpose digital computer systems. It is fabricated on a single LSI chip (see Figure 1·1). using Intel's n-channel silicon gate MOS process. The 8080 transfers data and internal state information via an 8-bit, bidirectional 3-state Data Bus (00-07). Memory and peripheral device addresses are transmitted over a separate 16- bit 3-state Address Bus (AO-A 15).
ARCHITECTURE OF THE 8080 CPU matically during every instruction fetch. The stack pointer maintains the address of the next available stack location in memory. The stack pointer can be initialized to use any portion of read·write memory as a stack. The stack pointer is decremented when data is "pushed" onto the stack and incremented when data is "popped" off the stack (Le., the stack grows "downward").
THE PROCESSOR CYCLE Arithmetic and Logic Unit (ALU): An instruction cycle is defined as the time required to fetch and execute an instruction. During the fetch, a selected instruction (one, two or three bytes) is extracted from memory and deposited in the CPU's instruction register. During the execution phase, the instruction is decoded and translated into specific processing activities.
be synchronized with the pulses of the driving clock. Thus, the duration of all states are integral multiples of the clock period. the contents of its Hand L registers. The eight-bit data word returned during this MEMORY READ machine cycle is placed in a temporary register inside the 8080 CPU. By now three more clock periods (states) have elapsed. I n the seventh and final state, the contents of the temporary register are added to those of the accumulator.
While no one instruction cycle will consist of more then five machine cycles, the following ten different types of machine cycles may occur within an instruction cycle: (1) FETCH (M1) (2) MEMORY READ (3) MEMORY WR ITE (4) STACK READ (5) STACK WRITE (6) INPUT (7) OUTPUT (8) INTERRUPT (9) HALT (10) basic transition sequence. In the present discussion, we are concerned only with the basic sequence and with the READY function. The HOLD and INTERRUPT functions will be discussed later.
/too Instructions for the 8080 require from one to five machine cycles for complete execution. The 8080 sends out 8 bit of status information on the data bus at the beginn ing of each machine cycle (during SYNC time). The following table defines the status information. Symbols INTA* STATUS INFORMATION DEFINITION Data Bus Bit Definition DO Dl STACK D2 HLTA OUT D3 D4 M, D5 INP* De MEMR* D7 o 9 D, D 8 27 D3 3 D, 4 8080 Acknowledge signal for INTE R R UPT request.
Till Gj_RESET READY+HLTA T2 121 <$.> HLTA READY. HLTA YES - NO READY ~_ I----------------<~ YES READY SET I NTE RNAL HOLD F/F 1 131 ~?____________ I HOLD I MODE I .J YES NO NO NO IlllNTE F/F IS RESET I F INTERNAL INT F/F IS SET. 1211NTERNAL INT F/F IS RESET IF INTE F/F IS RESET. 131SEE PAGE4-13. Figure 4-4.
The events that take place during the T3 state are determined by the kind of machine cycle in progress. In a FETCH machine cycle, the processor interprets the data on its data bus as an instruction. During a MEMORY READ or data must remain stable during the "data hold" interval (tDH) that occurs following the rising edge of the ¢2 pulse. Data placed on these lines by memory or by other external devices will be sampled during T3. a STACK READ, data on this bus is interpreted as a data word.
Ml Tl M2 T3 T2 T4 Tl M3 T2 T3 Tl T2 T3 _rL-"rL- rL.- h- rL- h-h- rL- rL- r-L_-.-1\ ~~ Wt Wt.JlJ t ----' BYTE ONE \. -'t----l SYNC -~ \ WAIT WR j DATA TO ACCUMULATOR \. I \ \ INP~T X ~J \. J -----, ~ J t ~I~ BYTE TWO FLOATING 1 1 DBIN READY 11- - - -- -- - I \UNKNOWNJ I . _J \ I \ '- "'" "'" "0" STATUS INFORMATION X0 18 NOTE: @ X0 Refer to Status Word Chart on Page 4-6. Figure 4-6.
"data output delay" interval (tOO) following the 1>2 clock's leading edge. Data on the bus remains stable throughout the remainder of the machine cycle, until replaced by updated status information in the subsequent T 1 state. Observe that a READY signal is necessary for completion of an OUTPUT machine cycle. Unless such an indication is present, the processor enters the TW state, following the T2 state.
INTERRUPT SEQUENCES In this way, the pre-interrupt status of the program counter is preserved, so that data in the counter may be restored by the interrupted program after the interrupt request has been processed. The 8080 has the built-in capacity to hand Ie external interrupt requests. A peripheral device can initiate an interrupt simply by driving the processor's interrupt (lNT) line high.
Mn T2 Tl Tw Mn+1 (TS )* (T4 )* T3 T Tl T2 ...... I'--OR ........., _h h n ~ h h n n h _--1tp f l --1 If-WL ~ UL --IrL ~U--L L--rL 1 ----- I FLOATING 1 I 1>]·0 HOLD REQUEST ----- --- -- ---I ----- ----- --- -- ---- I \.- ---) I -1 I'- T \ (1) -\ I HOLD READY I HOLD F/F INTERNAL I \ r\ II HLDA (1) SEE ATTACHED ELECTRICAL CHARACTERISTICS. *T4 AND TS OPERATION CAN BE DiNE INTERNALlY' I Figure 4-9.
HOLD SEQUENCES The S080A CPU contains provisions for Direct Memory Access (DMA) operations. By applying a HOLD to the appropriate control pin on the processor, an external device can cause the CPU to suspend its normal operations and relinquish control of the address and data busses. The processor responds to a request of this kind by floating its address to other devices sharing the busses. At the same time, the processor acknowledges the HO LD by placing a high on its HLDA outpin pin.
M, T, _n M2 T3 T2 T4 n n r1 T2 T, n h TWH r1 TWH h -~ ~ ~ ~ w---t. ~ ~ u----t. _~PC - - - - -- -~ SYNC -~ \ I OBIN - - --- - - - - -- I f--- I f---- I- - \ \ IT WAIT V8 STATUS INFORMATION ~0 I NOTE ® Refer to Status Word Chart on Page 4-6 Figure 4-11. HALT Timing TO STATE TW or T3 TO STATE T, TO STATE T, Figure 4-12.
M, Tn Tn+1 Tn+ 3 Tn+2 n n n i\ ----1L r--IL ----1L ----1 " Tn+i h ~ T2 n r1 ----1L ~----1L PC= 0 FLOATING ~~ - -- - " INTERNAL RESET T, rl ~ t::~ -- - - '--' RESET Tn+(;-1) -\ UNKNOWN I \ " ~ I SYNC r- DBIN " X0 " STATUS INFORMATION I1IWHEN RESET SIGNAL IS ACTIVE, ALL OF CONTROL OUTPUT SIGNALS WILL BE RESET IMMEDIATELY OR SOME CLOCK PERIODS LATER. THE RESET SIGNAL MUST BE ACTIVE FOR A MINIMUM OF THREE CLOCK CYCLES. IN THE ABOVE DIAGRAM N AND I MAY BE ANY INTEGER.
4-16
4-17
4-18
4-19
NOTES: 1. The first memory cycle (M 1) is always an instruction fetch; the first (or only) byte, containing the op code, is fetched during this cycle. 2. If the READY input from memory is not high during T2 of each memory cycle, the processor will enter a wait state (TW) until READY is sampled as high. 3. States T4 and T5 are present, as required, for opera· tions which are completely internal to the CPU.
Instruction Set 5 . :.' ~ , :" <,~~ ',',: :.\~~.~:.':'~ ',', ': ~'.,' ;.~; f~!;~r<.< ,("I, .
, I I I \ I
CHAPTER 5 THE INSTRUCTION SET 5.1 WHAT THE INSTRUCTION SET IS DDD,SSS A computer, no matter how sophisticated, can do only what it is instructed to do. A program is a sequence of instructions, each of which is recognized by the computer and causes it to perform an operation. Once a program is placed in memory space that is accessible to your CPU, you may run that same sequence of instructions as often as you wish to solve the same problem or to do the same function.
THE INSTRUCTION SET PC SP LABEL s p ~y 1\ + \JNN 16-bit program counter register (PCH and PCl are used to refer to the high-order and low-order 8 bits respectively). 16-bit stack pointer register (SPH and SPl are used to refer to the high-order and low-order 8 bits respectively). Bit m of the register r (bits are number 7 through 0 from left to right). 16-bit address of subroutine.
THE INSTRUCTION SET I Three-Byte Instructions Byte I One . 0 7 I I I I I I0 • Register Indirect - The branch instruction indicates a register-pair which contains the address of the next instruction to be executed. (The high-order bits of the address are in the first register of the pair, the loworder bits in the second.) The RST instruction is a special one-byte call instruction (usually used during interrupt sequences).
THE INSTRUCTION SET MOV r, M (Move from memory) (r) - ((H) (L» The content of the memory location, whose address is in registers Hand L, is moved to register r. 5.6 INSTRUCTION SET ENCYCLOPEDIA In the ensuing dozen pages, the complete 8085A instruction set is described, grouped in order under five different functional headings, as follows: 11 11 II I I ! I' I I o 1. Data Transfer Group - Moves data between registers or between memory locations and registers.
THE INSTRUCTION SET LHLD addr (Load Hand L direct) (L)-((byte 3)(byte 2» (H)-((byte 3)(byte 2) + 1) The content of the memory location, whose address is specified in byte 2 and byte 3 of the instruction, is moved to register L. The content of the memory location at the succeeding address is moved to register H.
THE INSTRUCTION SET STAX rp (Store accumulator indirect) «rp» - (A) The content of register A is moved to the memory location whose address is in the register pair rp. Note: only register pairs rp = B (registers B and C) or rp = 0 (registers 0 and E) may be specified. 0 R 0 P 0 0 ADD M (A) - XCHG 0 2 7 reg. indirect none (Exchange Hand L with 0 and E) The contents of registers Hand L are exchanged with the contents of registers 0 and E.
THE INSTRUCTION SET ADC M (Add memory with carry) (A) - (A) + «H) (L)) + (CY) The content of the memory location whose address is contained in the Hand L registers and the content of the CY flag are added to the accumulator. The result is placed in the accumulator. 0 0 0 Cycles: States: Addressing: Flags: 1 1 SUB M (Subtract memory) (A) - (A) - «H) (L)) The content of the memory location whose address is contained in the Hand L registers is subtracted from the content of the accumulator.
THE INSTRUCTION SET INR M (Increment memory) «H) (L) - «H) (L» + 1 The content of the memory location whose address is contained in the Hand L registers is incremented by one. Note: All condition flags except CY are affected. SBB M (Subtract memory with borrow) (A) - (A) - «H) (L» - (CY) The content of the memory location whose address is contained in the Hand L registers and the content of the CY flag are both subtracted from the accumulator. The result is placed in the accumulator.
TH E INSTRUCTION SET DAA (Decimal Adjust Accumulator) The eight-bit number in the accumulator is adjusted to form two four-bit Binary-CodedDecimal digits by the following process: 1. If the value of the lease significant 4 bits of the accumulator is greater than 9 or if the AC flag is set, 6 is added to the accumulator. 2. If the value of the most significant 4 bits of the accumulator is now greater than 9, or if the CY flag is set, 6 is added to the most significant 4 bits of the accumulator.
TH~INSTRUCTION SET 11 XRA M (Exclusive OR Memory) (A) - (A) -v- «H) (L)) The content of the memory location whose address is contained in the Hand L registers is exclusive-OR'd with the conteotof the accumulator. The result is P'taced in the accumulator. The CY and AC . ' .......e cleared. 1 o 1 o Cycles: States: Addressing: Flags: 1 1 1 o 2 7 reg. indirect Z,S,P,CY,AC XRI data (Exclusive OR immediate) (A) - (A).
THE INSTRUCTION SET ORA M (OR memory) (A) -- (A) V ((H) (L» The content of the memory location whose address is contained in the Hand L registers is inclusive-OR'd with the content of the accumulator. The result is placed in the accumulator. The CY and AC flags are cleared. CMP M (Compare memory) (A) - ((H) (L) The content of the memory location whose address is contained in the Hand L registers is subtracted from the accumulator. The accumulator remains unchanged.
THE INSTRUCTION SET RRC CMA (Rotate right) (An) - (An + 1); (A7) - (Ao) (CY) - (Ao) The content of the accumulator is rotated right one position. The high order bit and the CY flag are both set to the value shifted out of the low order bit position. Only the CY flag is affected. o o o 0 Cycles: States: Flags: RAL The contents of the accumulator are complemented (zero bits become 1, one bits become 0). No flags are affected.
THE INSTRUCTION SET 5.6.4 Branch Group This group of instructions alter normal sequential program flow. Condition flags are not affected by any instruction in this group. The two types of branch instructions are unconditional and conditional. Unconditional transfers simply perform the specified operation on register PC (the program counter). Conditional transfers examine the status of one of the four processor flags to determine if the specified branch is to be executed.
THE INSTRUCTION SET Ccondition addr (Condition call) If (CCC), «SP) - 1) - (PCH) «SP) - 2) - (PCl) (SP) - (SP) - 2 (PC) - (byte 3) (byte 2) If the specified condition is true, the actions specified in the CAll instruction (see above) are performed; otherwise, control continues sequentially. I 1 1 I.
THE INSTRUCTION SET The content of register A is moved to the memory location whose address is one less than register SP. The contents of the condition flags are assembled into a processor status word and the word is moved to the memory location whose address is two less than the content of register SP. The content of register SP is decremented by two. (Jump Hand l indirect move Hand l to PC) (PCH) - (H) (PCl) - (l) The content of register H is moved to the high-order eight bits of register PC.
THE INSTRUCTION SET SPH L (Move H L to SP) (SP) - (H) (L) The contents of registers Hand L (16 bits) are moved to register SP. POP PSW (Pop processor status word) (CY) - «SP))o (P)- «SP))2 (AC)- «SP))4 (Z) - «S P))6 (S) - «SP))7 (A) - «SP) + 1) (SP) - (SP) + 2 The content of the memory location whose address is specified by the content of register SP is used to restore the condition flags. The content of the memory location whose address is one more than the content of register SP is moved to register A.
THE INSTRUCTION SET EI (Enable interrupts) The interrupt system is enabled following the execution of the next instruction. Inter· rupts are not recognized during the EI instruction. 1 1 1 o 1 Cycles: States: Flags: 1 o 1 RIM 1 4 none (Disable interrupts) The interrupt system is disabled immedi· ately following the execution of the 01 in· struction. Interrupts are not recognized during the 01 instruction.
THE INSTRUCTION SET SIM (Set Interrupt Masks) (8085 only) The execution of the SIM instruction uses the contents of the accumulator (which must be previously loaded) to perform the following functions: • Program the interrupt mask for the RST 5.5, 6.5, and 7.5 hardware interrupts. • Reset the edge-triggered RST 7.5 input latch. • Load the SOD output latch. To program the interrupt masks, first set accumulator bit 3 to 1 and set to 1 any bits 0, 1, and 2, which disable interrupts RST 5.5, 6.5, and 7.
8085A 8080Al8085A INSTRUCTION SET INDEX Table 5·1 Code Instruction Bytes T States BOB5A BOBDA Machine Cycles Instruction Code Bytes T States BOBSA BOBDA Machine Cycles ACI DATA CE data 2 7 7 FR LXI RP,DATA16 OORP 0001 data16 3 10 10 FRR ADC REG 1000 lSSS 1 4 4 F MOV REG,REG 0100 DSSS 1 4 5 F* ADC M 8E 1 7 7 FR MOV M,REG 01110SSS 1 7 7 FW ADD REG 10000SSS 1 4 4 F MOV REG,M 01000110 1 7 7 FR ADD M 86 1 7 7 FR MVI REG,DATA 00000110 data
SOSSA 8085A CPU INSTRUCTIONS IN OPERATION CODE SEQUENCE Table 5·2 II· \ ,I OP CODE 00 01 02 03 04 05 06 07 08 09 OA OB OC OD OE OF 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A MNEMONIC NOP LXI STAX INX INR DCR MVI RLC B,D16 B B B B B,D8 - DAD LDAX DCX INR DCR MVI RRC B B B C C C,D8 LXI STAX INX INR DCR MVI RAL D,D16 D D D D D,D8 - DAD LDAX DCX INR DCR MVI RAR RIM LXI SHLD INX INR DCR MVI DAA D D D E E E,D8 H,D16 Adr H H H H,D8 DAD H LHLD Adr OP CODE 2B 2
808SA 8085A INSTRUCTION SET SUMMARY BY FUNCTIONAL GROUPING Table 5·3 Mnemonic Description D7 D6 Instruction Code (1) D5 D4 D3 D2 Dl DO Page Mnemonic Description 5·4 5·4 5-4 5-4 5·4 5·5 CZ CNZ CP CM CPE CPO Call on zero Call on no zero Call on positive Call on minus Call on parity even Call on parity odd D7 06 Instruction Code (1) D5 D4 D3 02 DIDO Page MOVE, LOAD, AND STORE MOVrl r2 MOVM.r MOVr.
808SA 808SA INSTRUCTION SET SUMMARY (Cont'd) Table 5·3 Mnemonic Description S81 Instruction Code (1) D5 D4 D3 D2 Page Mnemonic Description Subtract immediate from A with borrow 5·8 RRC RAL Rotate A right ANA r • And register with A XRA r Exclusive with A 5·9 5·10 ORA r a R register with A 5·10 CMPr ANA M Compare register with A And memory with A Exclusive OR memory with A OR memory with A Compare memory with A 5·11 D7 D6 D1 DO LOGICAL XRA M ORA M CMPM ANI XRI ORI CPI aR register
Device Specifications 6
inter 8080A/8080A·1/8080A·2 8·BIT N·CHANNEL MICROPROCESSOR • TTL Drive Capability • 16·Bit Stack Pointer and Stack Manipulation Instructions for Rapid Switching of the Program Environment • Decimal, Binary, and Double Precision Arithmetic • 2 lAS ( - 1:1.3 lAs, - 2:1.
inter 8080Al8080A·118080A·2 Table 1. Pin Description Symbol Type Name and Function A1S;Ao 0 Address Bus: The address bus provides the address to memory (up to 64K 8-bit words) or denotes the I/O device number for up to 256 input and 256 output devices. Ao is the least significant address bit. Dr Do I/O Data Bus: The data bus provides bi-directional communication betweeen the CPU, memory, and I/O devices for instructions and data transfers.
8080Al8080A·1/8080A·2 ABSOLUTE MAXIMUM RATINGS· "NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Temperature Under Bias . . . . . . . . . . . .
8080Al8080A·1/8080A·2 A.C. CHARACTERISTICS (8080A) Symbol (TA = O°C to 70°C, VOO = +12V ±5%, Vee = +5V ±5%, Vee = -5V ±5%, Vss =OV; unless otherwise noted) Parameter ·1 ·1 ·2 ·2 Min. Max. Min. Max. Min. Max. Unit 0.48 2.0 0.32 2.0 0.38 2.
8080A/8080A·1/8080A·2 WAVEFORMS °2 A,.-AO ------+-~ ----------t---''f- --+......11 SYNC _ _ _ _ _ _ _ _ DBIN ---------------------~......I .2>-+--+=~ --+t-I:!: 111~1' ~ -I WAIT ---------------:.;....H---..;.;.--+-1. _ READY - I I 'RS - - - toe·--+- 4-- 'H - - +--; ~-=:1~ --:11 l~--+t--I ill ---r t H ·.., ,.... - 1".-.
inter !1 8080Al8080A·1/8080A·2 WAVEFORMS (Continued) NOTES: (Parenthesis gives -1, -2 specifications, respectively) 1. Data input should be enabled with DBIN status. No bus conflict can then occur and data hold time is assured. tOH = 50 ns or tOF, whichever is less. 2. tCY = t03 + tr2 +t,p2 + tf2 + t02 + tr1 ;;. 4BO ns ( - 1 :320 ns, - 2:3BO ns). TYPICAL A OUTPUT DELAY VS. A CAPACITANCE >- ~ o I- 12 I:::l o.., +100 ..\ CAPACITANCE (pI) (CACTUAL - CSPEC ) 3.
inter 8080Al8080A·1/8080A·2 INSTRUCTION SET increment and decrement memory, the six general registers and the accumulator is provided as well as extended increment and decrement instructions to operate on the register pairs and stack pointer. Further capability is provided by the ability to rotate the accumulator I~ft or right through or around the carry bit.
inter I~ 8080Al8080A·118080A·2 !II1 Table 2. Instruction Set Summary Operations Description Instruction Code [1] Mnemonic [ry 06 Os 04 03 02 01 DO MOVE, LOAD, AND STORE MOVr1,r2 0 1 0 0 0 MOVM,r.
inter 8080A/8080A·1/8080A·2 Summary of Processor Instructions (Cont.
intJ SOSSAH/SOSSAH-21S0SSAH-1 S-BIT HMOS MICROPROCESSORS • Single +SV Power Supply with 10% Voltage Margins • On-Chip System Controller; Advanced Cycle Status Information Available for Large System Control • Four Vectored Interrupt Inputs (One is Non-Maskable) Plus an SOSOA-Compatible Interrupt • Serial In/Serial Out Port • Decimal, Binary and Double Precision Arithmetic • Direct Addressing Capability to 64K Bytes of Memory • Available in EXPRESS - Standard Temperature Range - Extended Temperature Range •
8085AH/8085AH-2/8085AH-1 Table 1. Pin Description Symbol ADO_7 ALE Type Name and Function o Address Bus: The most significant 8 bits of the memory address or the 8 bits of the I/O address, 3-stated during Hold and Halt modes and during RESET. I/O Multiplexed Address/Data Bus: Lower 8 bits of the memory address (or I/O address) appear on the bus during the first clock cycle (Tstate) of a machine cycle. It then becomes the data bus during the second and third clock cycles.
intJ 8085AH/8085AH-2/8085AH-1 i1 \1" I :1 Table 1. Pin Description (Continued) ,-------,-----,----------------------, Symbol Name and Function Type Name and Function Symbol Type I Trap: Trap interrupt is a nonmaskable RESTART interrupt. It is recognized at the same time as INTR or RST 5.5-7.5. It is unaffected by any mask or Interrupt Enable. It has the highest priority of any interrupt. (See Table 2.) RESET OUT a Reset Out: Reset Out indicates cpu is being reset.
8085AH/8085AH-2/8085AH-1 FUNCTIONAL DESCRIPTION The three maskable interrupts cause the internal execution of RESTART (saving the program counter in the stack and branching to the RESTART address) if the interrupts are enabled and if the interrupt mask is not set. The nonmaskable TRAP causes the internal execution of a RESTART vector independent of the state of the interrupt enable or masks. (See Table 2.) The 8085AH is a complete 8-bit para"el central processor.
inter 8085AH/8085AH-2/8085AH-1 Parallel resonance at twice the clock frequency desired C L (load capacitance) :0:::; 30 pF Cs (shunt capacitance) :0:::; 7 pF Rs (equivalent shunt resistance) :0:::; 75 Ohms Drive level: 10 mW Frequency tolerance: ± .005% (suggested) INSIDE THE EXTERNAL TRAP INTERRUPT REQUEST RESET IN 8085AH TRAP SCHMITT TRIGGER RESET +5V Note the use of the 20 pF capacitor between X2 and ground.
8085AH/8085AH-2/8085AH-1 X, B085AH ----, +5V I I I ...L LOW TIME> 60 n8 4700 CINT ~ 15 pF TO 1KO 'T" I I / x, X2 _ _ _ --1I a. Quartz Crystal Clock Driver 8085AH x, ----, I I ...J.... ·X2 LEFT FLOATING d. 1-6 MHz Input Frequency External Clock Driver Circuit CINT ~15pF T X2_ _ _ I -.J +5V LOW TIME> 40 ns .mil / b. LC Tuned Circuit Clock Driver .,.....------1 X, 8085AH x, f" 4700 \...--_6K_--t e. 1-12 MHz Input Frequency External Clock Driver Circuit c.
8085AH/8085AH-2/8085AH-1 As in the 8080, the READY line is used to extend the read and write pulse lengths so that the 8085AH can be used with slow memory. HOLD causes the CPU to relinquish the bus when it is through with it by floating the Address and Data Buses. ---- SYSTEM INTERFACE - The 8085AH family includes memory components, which are directly compatible to the 8085AH CPU.
8085AH/8085AH-2/8085AH-1 J\ A8-15 T"'V ) /1 ADO·7 'J 8085AH A /). ALE """""- RD WR 101M ClK RESET OUl r READY i i • Vee Vee I--- ~~~~--~--~+--I-V~-vee I I. RESET I· TIMER IN WR RD 'Z 7A1'~'\707 A8- 101M ALE AD _ 101 _I."" I CE MALE RDlowelKRST!RDY 8355 [ROM + I/O] OR 8755A [PROM + I/O] 8156H [RAM + I/O + COUNTERITIMER] 88 Figure 8.
intJ 8085AH/8085AH-2/8085AH-1 II'I.', I I" BASIC SYSTEM TIMING I'!I Table 3. 8085AH Machine Cycle Chart The 8085AH has a multiplexed Data Bus. ALE is used as a strobe to sample the lower 8-bits of address on the Data Bus. Figure 10 shows an instruction fetch, memory read and I/O write cycle (as would occur during processing of the OUT instruction). Note that during the I/O write and read cycle that the I/O port address is copied on both the upper and lower half of the address.
SOS5AH/SOS5AH-2/S0S5AH-1 ABSOLUTE MAXIMUM RATINGS· *NOTlCE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Ambient Temperature Under Bias .........
8085AH/8085AH-2/8085AH-1 A.C. CHARACTERISTICS (Continued) Symbol Parameter 8085AH[2] (Final) Min. tAll AO-7 Valid Before Trailing Edge of ALE Max. 90 8085AH-2[2] (Final) Min. Max. 50 220 8085AH-1 (Preliminary) Min. 25 100 Units Max.
8085AH/8085AH-2/8085AH-1 3. For all output timing where CL =f 150 pF use the following . correction factors: 25 pF ~ CL < 150 pF: -0.10 ns/pF 150 pF < CL ~ 300 pF: +0.30 ns/pF 4. Output timings are measured with purely capacitive load. 5. To calculate timing specifications at other values of tCYC use Table 5. NOTES: 1. Aa-A15 address Specs apply 101M, SO' and Sl except Aa-A15 are undefined during T4-Ts of OF cycle whereas 101M, SO, and Sl are stable. 2.
8085AH/8085AH-2/8085AH-1 WAVEFORMS CLOCK X, INPUT ClK OUTPUT ------.. tXKF ........-- READ T, ClK T2 1 \~-----J/ 1 T3 ~~----,r--\,-------,/ -4------ tLcK---+--1 T, I \ I. tCA -I ADDRESS ,--- tel _ _- - - ALE RD/INTA WRITE 5 ). I---7 ) I- X ADDRESS ADDRESS i-- L tlDW- >--. 1 - DATA OUT tow tLL _ I ----- tLA-----I AL E tCA X +--twD-1 I--- tWDL 1/ I - - t AL - _ ' LC i----- HOLD 'AC \ HOLD . . - t Cl ----+- =1 T2 ClK ICC ~ WR THOLO T3 \ / t \ .
8085AH/8085AH-2/8085AH-1 WAVEFORMS (Continued) READ OPERATION WITH WAIT CYCLE (TYPICAL) TO WRITE T, SAME READY TIMING APPLIES T, T, T3 _ t e A ___ AS "A 15 ~~----4-------------4-------------~I~--------------+-----~----- •.-./--- I I I ----- - - -- 'LA tAFR 'RD ICC ~~L~_;l~Ry~l"---+--------m...- - - - - - - ; I > --~tAC- - -tARY-- READY NOTE 1 READY MUST REMAIN STABLE DURING SETUP AND HOLD TIMES. INTERRUPT AND HOLD -~.
intJ 8085AH/8085AH-2/8085AH-1 Table 6. Instruction Set Summary Mnemonic I D7 D6Instruction Code Ds D4 D3 D2 D1 Do Operations Description Instruction Code Mnemonic D7 D6 Ds D4 D3 D2 D1 Do MOVE, LOAD, AND STORE MOVr1 r2 MOVM.r MOVr.
8085AH/8085AH-2/8085AH-1 I Table 6.
808SA/808SA-2 SINGLE CHIP 8-BIT N-CHANNEL MICROPROCESSORS • +5V Power Supply • Single 100% Software Compatible with SOSOA ..• • • 1.3 p,s Instruction Cycle (SOS5A); O.
inter 8085A/8085A-2 *NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS* Ambient Temperature Under Bias .........
I.... II inter II 808SA/808SA-2 A.C. CHARACTERISTICS (TA = O°C to 70°C, Vee = ov ±5%, vss = OV) Symbol 8085A·212J 8085AI2J Parameter Min. Max. Min. Max. 2000 200 40 2000 Units I, I tCYC t1 ClK Cycle Period ClK low Time (Standard ClK loading) 320 80 t2 . ClK High Time (Standard ClK loading) 120 tnt, tXKR t yle !: t AC t ACL tAD tAFR tAL tALL t ARy tr.
intJ 8085A18085A·2 A.C. CHARACTERISTICS (Continued) Symbol 8085A(2) Parameter Min. tRAE 8085A·2(2) Max. Min. 150 Trailing Edge of READ to Re·Enabling of Address Units Max.
II I
Appendix Applications of MCS®-85
APPENDIX 1 AP.PLICATIONS OF MCS-85™ SECTION 1 INTRODUCTION TO MCS-85™ APPLICATIONS When the first microprocessor was introduced about five years ago, it was largely ignored by the electronics industry. However, since that inasupicious beginning, this new device has become the hottest topic in current technology. As more and more product designers become familiar with the capabilities of microcomputers, the number of new applications increases geometrically.
MCS-85™ APPLICATIONS Sample Applications Calculating Oscilloscope Blood Analyzer Programmable Video Game Process Control System Line Printer APPLICATION Intelligent Terminals Gaming Machines Cash Registers Accounting and Billing Machines Telephone Switching Control Numerically Controlled Machines Process Control Intelligent Terminal N.C.
MCS-85™ APPLICATIONS l ,I r TRANSMITJ INTERFACE RECEIVE INTERFACE n Vec 111J ex: 1 C X1~ ~ c 8085A ::l c- .'"".1:"" 0 ~ Go 0 :5u ~ ....
M_C_S_-S_5_TM_A_P_P_L_I_C_A_T_IO_N_S_ _ _ _---------:l~ ____ J2 _ _ _ _ _ _ _ _ '1 2 READY III 1'1 I j I,' :~ R4 ~ R5 47 vv J7 13 25 TX TX RET I I I I I I I I I I I I I I I I I RX RX RET UR' I 3K -10V eLK 1,1' WRI RDI I I, RST ALE I' I , 101M I I .: i R11 100 C5 Y1 1/2WT1/-lf 12 24 Q1 2N2907 vvv I I ~ 2N2907 Q2 R8 430 1W I I I R6 2.7K 1K ~ 5.1K R2 .> R7 .>200 • 1W .--R3 40_t ~ RDY I lD~ X1 X2 SOD > 1.
MCS-85™ APPLICATIONS H ,I 1 W I l t t40 '~~voov~ov~-~ ", r" I' 13 1 :~ A14 "'~ 3 ~ AD 17 : 18 6 J3 24 PA ~ ~ ~ ~ 26 ~~ 3 4 29 1~ 7 10 CLK 4 ~ -¥- 30 7 31 -fa ,..:.;;..., + ~ :! r~ 11 ALE 7 21 101M 22 ~ ~~ ~ CSO 37 38 6 7 39 :~ 'I ." 14 1 2 15 3 16 4 17 5 18 6 8755A AD ~ 4 RD ~ lolM A8 A9 Al0 PB 4 5 6 7 8CE 13 1 :: 2 16; 17 5 18 6 19 7 f~ 1 2 3 4 5 6 AD PB ~~~ PC 19 18.,(-),,17 -- I 3 ~ ~ ~ 25 26 27 28 ,..g.. ~ ~ ~ ~ r14,..g...
MCS-85™ APPLICATIONS Small System The schematic in Figure 3 is of a complete microcomputer with only 6 ICs. The system contains its own serial 1/0 communication lines, multi-level interrupt, two programmable timers, and power-on reset. System capacity is 512 bytes of RAM, 4K bytes of PROM, and 76 lines of programmable 1/0. Vss Vcc ~ ~ Block Move, Block Search In a large system application high speed block moves may be necessary.
MCS-85™ APPLICATIONS pointed-to location in the block. When Port A equals Port B, the output of the cqmparator will gate off the DMA request. The requesting program can now read the Channel 2 address which is pointing to the search value plus one. However, if the status register of the 8257 indicates that TC of Channel 2 has been reached, then no match was found.
SECTION 2 DETAILED APPLICATION EXAMPLES As an example let's look at Intel's ROM/EPROM family (Fig. 7) and develop a system block diagram. This system should allow upward compatibility for these particular devices and avoid any bus contentions due to undefined addresses. In Figure 8 a traditional decoding scheme is shown that uses the time difference between tacc (address access) and tco (chip select access) to allow for decoding of the EPROM/ROM to be selected.
! - -L ADDRESS '--- EPROMi ROM = 1 L r-r- --- EPROMi ROM = 2 - - L = - L EPROMi ROM '--- r-- 3 EPROMi ROM = 4 - r- CS 1 CS 2 CS 3 CS 4 I I I I '---- DATA .J - --- I DECODE POSSIBLE BUS CONTENTION / I A S. 1S I ADO•7 8212 ADDRESS LATCH Vee ~ Ao . -1- I I 8085A - As . AlO ALE "'" 0 0 .7 - r,~ I- PDiPGM ~ GS A 11 .
II ADDRESS EPROM I ROM #4 ; CONTROL DATA ~ j '-'--- DECODE I A g.15 1 ADO.7 8212 ADDRESS LATCH Vee - As' A 10 ALE 8085A R5 l I- I OE QUALIFIES +5V ~ ~ 101M I ADDRESS SELECTION ~ / ~ A7 2716 DATA OUT OF 2716 As ~ ~ ~ ~ ~ ~ Ao· 0 0.
STATIC MEMORIES Addresses The lower 14 addresses (AO-A13) are used to select one of the 16,384 8-bit bytes in each 16K byte data bank. The lower 8 of these 14 addresses (AO-A7) flow through an 8212 and are latched by ALE, effectively demultiplexing the address/ data bus. These lower 8 addresses with the next 6 (AS-A13) enter the 3242 multiplexer/refresh controller. The Row Enable of the 3242 controls which half of the addresses are presented to the dynamic RAM memory.
r--- +5V !--;; , ~ , 48-64K OO,-OOS 8212 32-48K OI,-OIS Vee I, L..-- 64K x 8 2117 ARRAY 16-32K +5V +5V ~O EJ EJ EJ r--- Q 2117-4 A!,O AD7 ~ A'5 L....--.. 1---.---""''- ALE ~ HLOA CLK N s, 8085A 101M IIIIII WR R5 r<1 Cs RESET x, 8216 OiEN X2 ~AA~ -4~ru~1 ~ r<1cs .. L....r 47011" '804 +5V 24.
Data The data path to the 2117s is through two sets of buffers to account for memory being off board. To determine bus timing it is helpful to know that Write data is not guaranteed to be valid from the BOB5A until 40 ns after the leading edge of the write control signal. On account of this and the delay times for the buffers it i~ecessary to delay the cycle request on a write until the WR signal goes low. The solution shown still does not require wait states. An inhibit memory signal is also involved.
11. \'11 During initialization: MVI A, D5H OUT TIMER MSBYTE MVI A, A4H OUT TIMER LSBYTE MVI A, COH OUT TIMER COMMAND Program i SET TIMER COUNT TO 5550* FOR REFRESH COUNT 1 INTERRUPT CPU AT TO (TIMER OUT) CALL RFRS (REFRESH SERVICE) LXIHL,O DADSP LXI Sp, 0080 SAVE STACK POINTER IN HL 32K - 48K REFRESH POP BC POP BC REFRESH, DUMMY READ 64 TIMES 20 690 I I I START COUNTER, PLACE CO IN 8155 STATUS REG. AT RST 7.
,I A1 5 A8 .--11 ALE r---- -f D08--DOl STB DS2 8212 MD CUi VCC ~ '- I I ADO B08SA 7~ RD 74LS36~ J I ~~ ~ I -1>-=11 WR ~~ 74LS04 D-~ r---- MEMR lOR MEMW CHIP SELECT => HOLD HLDA CLK(OUn r------ RESET RESET OUT f--- '~ 74LS04~ - - ~ D,7 r---- MEMR r---- lOR MEMW r-- lOW A'7 I - - - I DO 8237 MEMR DREao DACKO MEMW DREOl lOW DACKl ~ HRa DACK2 DRE02 r-----2- HLDA r---E-- CLK DREa3 DACK3 EOP RESET AEN DS2 I DI8 I I Dll Figure 12.
SYSTEM TIMINGS seen that the rising edge of the X1 input causes flip·flop A to toggle. From this flip-flop two internal signals are generated that drive all functions in the SOS5A, A-2 and produce the output control signals and clock. Referring to Figure 15, it is seen that clock output is derived from the internal <1>1 signal in the schematic of Figure 14. This output Signal is a MOS output unlike the bipolar outputs of the S224 in the SOSOA system.
I Tl ---T2 T3 Xl (INTERNAL) r ':'2 elK OUT ALE ADDRESS AS.15 STATUS RD, mi, INTA 91 ADDRESS ADO·7 ADDRESS DATA Figure 14. Clock In (X1) to Output Relationship Xl INPUT "'O"T~_ i ~1""-~~~~~~~tCYC ~~~------i.r~Figure 15.
I', i!l"I." I 1---------Tl--------~--------T2--------~--------T3--------1 I' II, !I elK OUT I' ALE ADDR8-15 STATUS ADO·7 (READ MODE) ADO·7 (WRITE MODE) Figure 16. 8085A·2 Clock Related Timing 3.125 vs. 5 MHz Considerations The SOB5A (with maximum internal clock frequency of 3.125 MHz) and SOS5A-2 (5 MHz) have some differences in their bus operation. There are two sets of peripherals that can be used with both the SOS5A and A-2.
3.
Memory Device Compatibility Determining What Memory to Select For Your Application When developing a system which will use sufficient memory to require buffering (see the capacitive loading section to determine when it is needed), it is important to understand how to select the slowest, lowest cost memory and still be compatible with the bus timings with minimum wait states.
For minimum 8085A timing 8085A-2 timing tAD MEMORY = tAD8085A - (8282 + 8205 delay) - (8286 delay) + transitional gain due to buffering* = tAD85 - (TIVOV + t--) - (TIVOV) + tCAPB * Therefore for tLDR: tLDR MEMORY = tLDR 8085 - (buffer delay) - (8205) = (5/2+N)T - 225 - 55 - 35 + 15 = (5/2+ N)T - 300 (for 8085A) (5/2+N)T - 225 (for 8085A-2) - (8286) + tCAPB tLDR-(delay)-(t--)-(TIVOV)+tCAPB = 2T -180 -30 -20 -35 +15 = 2T - 250 for 8085A = 2T -200 for 8085A-2 = where N = number of wait states and T = cyc
In general, tAD MEM and tLDR MEM are the parameters needed for chip enabling, selection and address access times, and probably are the most important considerations when determining which memory device to use. When there is an output enable, tRD MEM is also used. All relevant access times must be met by the resulting system configuration to be compatible. This note will not attempt to generalize a procedure that deals with the interface to dynamic RAM, but the 2117 example shown earlier is described below.
TAKEN FROM 2117-4 DATA SHEET WRITE CYCLE MIN tRC tRAS tCAS tWCS tWCH tWCR tWP tRWL tCWL tDS tDH tDHR 410 ns 250 ns 165 ns -20 ns 75 ns 160 ns 75 ns 100 ns 100 ns o ns 75 ns 160 ns DYNAMIC RAM CONFIGURATION MAX MAX MIN 720 307 198 34 164 287 205 205 205 23 Data Data ns ns ns ns ns ns ns ns ns ns •• held until next cycle held until next cycle •• Data is not valid from the 8085A until 40 ns after WR falls. I Table 4.
Part No. AC. Parameter Min. (ns) Max.
The timing specs of the 8085A are guaranteed as long as the 150 pF maximum loading is not exceeded, which includes the wires, components and parasitics. If the user exceeds this value and wants to guarantee his system timing he must either derate the system timings or use buffering. Taking note of asterisked margins shown on the comparison sheet: tAD, tRD, tRR and tDW, it is seen that they are all taken care of by introducing a wait state.
APPLICATION EXAMPLE 1 MINIMUM SYSTEM APPLICATION AS A TEMPERATURE SENSOR nents are on the same board and far below the maximum component loading. A monostable multivibrator (74121) is also shown with a thermistor connected to RE/CE. Overview Following is an application example that illustrates the use of the interrupt and SOD pins on the 8085A, software for a block search routine, and the procedure for using and reading the 8155 counter.
7 11 4 9 GND 111[' NC-g Ri 74121 0 B CE .111 F~ NC 12 RE/CE NC NC---;J NC +5 ---;:t Vee ~ T 1 NC 4 5 A2~ 8085A 8 -::=-5 ~ P:Bo PB7 9 TO VECTOR INTR 7 36 ""6 CLK (OUT) RST 5.5 ~ RST 7.5 A;o 0 RESET IN INTA Vee 40 1 ROY f6 3 --to Vss 31 37 8155 .. /5 ~ -- ~ S07 S1 7 Vss -- go 8205 Ao-A2 00 El-E2 Vss ~ 3 ~+5 E3 Vee 0, 02 10 9 05 r--- 4 06 11 04fl 03 7 12 8 21 3 22 .. FROM KEYBOARD \ 4 74LS156 ':I +5 2YO-2Y3 le 2C 5"""" .......
I.~ Software 1. The user can not use the initial value of 1 to detect only one pulse. The software (at end of section) for this application illustrates several features of ·the 8085A, such as the programming of the SOD line, interrupts and 8155 counter. Additionally, an example of a block search routine is illustrated. I I, ~i I 2.
'~ Ii ri I' 179-199 CODE LINES 18-23 ,t 28-32 I"~ Ii ~ 36-37 118-144 42-47 79-82 101-105 Figure 21.
THERMISTOR START WITH 3FFE H DEG.C OHMS (.7) (.1,u) (R T) APPROX. TIME (ms) APPROX. COUNT LEFT (HEX) 20 12,490 .874 3585 21 11,940 .836 35FA 22 11,420 .799 366A 23 10,920 .764 3605 24 10,450 .732 373A 25 10,000 .7 3772 26 9,573 .670 3700 = 27 9,167 .642 3840 w m m 28 8,777 .614 38A1 29 8,407 .588 38F1 '" ~ j.IO~~ .. '" oilJ",,,' .. te., i'r .. u~· ," """' ...... , '" ~!.lnj .. "1 'led ·p"~I .. nrp '.""'''".Jl- ' .. ,urv .. I"~ )".01'''10( ,,'('0,1" I :,~.
For an example with N = 256, CC = .32 f.Lsec at 3.125 MHz; Byte time = 6.7 f.Lsec. A match search routine with minimum memory usage is given below: Search Cmp M RZ INX H OCR C JNZ search STC RET compare byte return if match else increment pointer has the entire block been searched? If so set no match flag and return. Once the count less than match is found in the application the HL register has 10 added to it which points it at the corresponding temperature (lines 79-82).
I" 11," Ii APPLICATION EXAMPLE 2 CRT INTERFACE I I I Most microprocessor systems require some sort of serial communications. This may be selected for reasons of economy (to reduce the number of interconnections required in a distributed system), or it may be necessary in order to communicate with such common peripherals as CRT's or teletypewriters. The algorithm for receiving serial code involves sampling the incoming data at the middle of each bit time.
+6V 14 N.C. SID 6 Jl 2 CRT DATA OUT 3 CRT DATA IN 10 12 11 SIGNAL GROUND 13 o 0 0 0 0 000 0 0 0 00000000 0 0< 0 MCI489 7 "::" +12V -12V 8086 SOD 4 10...----....__ 330pF 121--.....----... 13...----....__ MCI488 GNDr~~------------~--------~--~ Figure 23. RS·232C Interface Schematic Upon power-up or reset, or when the console device baud rate is changed, the baud rate identification subroutine (BRIO) is called.
SOD are ideal for many applications which involve critical I/O timing, the timing techniques used here may be of interest to software designers. Accordingly, the mathematical derivation of the timing parameters is included in this analysis, as well as a justification for the BRID algorithm. The algebra involved might be a bit too tedious for designers unconcerned with generating software delays.
POP H POP !? Otherwise, continue. Rotate the data bit right into register C, and repeat the cycle: EI RFT INPUT ROUTINE I The console input routine uses the opposite procedure; instead of moving a bit from register C to the CY, then to A7, then to SOD, CIN loads a bit from SID into A7, then moves it to CY, then into register C. I' First, set up the CPU as before: ~~ I PUSH PI !,!\,1I B.:? RIl'l ')PA m LHU' HALFPrT <4> [:ofF.' DCP L (12 H ..TN: CI2 mz ..Tt1P CE <113::' <.
f \: I:, 1",1.,'.' desired. This guarantees that at rates up to 9600 baud, where each bit time is at least 104 fJsec wide, some value of BITTIME can be found which will be accurate to within 2.2%. For a typical calculation, see the example below. EXAMPLE To produce 2400 baud with the standard 6.144 MHz crystal: (6.144 X 10 6) + 2 2400 83 + 14 (HO 14 (HO (6.144 X 106 +2) (HO' [( 2400 BAUD RATE IDENTIFICATION ROUTINE The function of BRID is to compute the appropriate parameters BITTIME and HALFBIT.
I ing signal is zero. BITTIME is then obtained by individually incrementing registers Hand L. To obtain HALFBIT, divide the value of (HU' determined above by two before incrementing each register. Otherwise continue. Store HL temporarily for the HALFBIT calculation. Obtain and store BITTIME: PUSH In order to implement this algorithm, set HL to -6, verify that the incoming signal is a logic one, then wait for the start bit transition. BP.ID: BP.
APPLICATION EXAMPLE 3 CASSETTE RECORDER INTERFACE circuit is shown in Figure 26, using one LM324 quad op amp and a few standard value discrete components which should be available in even a digital design laboratory. On playback, analog circuitry is again used to detect the presence of a tone burst. In Figure 26, A2 buffers the incoming signal, and A3 inverts it. The peaks of these two signals are transmitted through 0 I or 02 and are filtered by an RC network.
I VOH SOD OUTPUT VOL TIME DATA "0" DATA"'" Figure 25. Tape Interface Data Recording Scheme 0---- ~--~~--~------------~~~--------------~------------------~soo 8085 o ">--------=-----ISIO NOTES: Al - A4: % LM324 QUAD OP AMP ANY LOW CURRENT DIODE ALL RESISTORS ±5% 01 - 02: Figure 26.
It VOH lUI @ VOL ® @ 3V '-..r\.J 1V \'1 I':· Rotate register C through CY: \--TONE BURST---I MOil RAR R.• C MOIl C, fI \' I ... I, i Move CY to the SOD enable bit position, A6. Simultaneously set A7 to one, and clear all other bits. Output a tone burst or space, depending on the previous contents of CY: GND - - - - - - , ( RECORDING OR TRANSMISSION MEDIUM) Mill RAR RAR CALL +1V @ GND----~ -1V @ Clear the accumulator, and output a space: 2.
'-I" I, I, i,' ~' burst is being received when TAPEIN is called, wait until the burst is over: Continue until the last bit has been received: 1'1 TAPEIN: Mill TI1: B,8 ~1\lI O. eeH CflLl SiTIN JC TIl CALL JC SIiIN CFlLL .
The CRT and Cassette Code also includes a simple block record routine utilizing TAPEO. Before calling BLKRCD, HL must be set to the start of the desired block, and the recorder turned on manually. Successive bytes will be recorded until the end of that page, i.e., until L is incremented to zero. The playback routine requires presetting HL to the target address and turning on the recorder before PLA YBK is called.
1', ,I 1 , , t t i t sion rates, as computed for the selected crystal freq uency. Initialization would req uire the operator to hit a specific key several times (usually the "U" key, which generates a pattern of alternating ones and zeros). The identification routine would attempt to "read" this pattern at each baud rate, in turn, until finding the rate at which the read was successful. components in the analog interface might also be modified.
Temperature Sensor Code \1 III iI ~' 1 I,' II I, ASI!88 :F1: TEST. SRC IlOO85 \ ISIS-II 8888/8885 IR:RO RSSEI'IBlER, V2. {I I I LOC (EJ SEQ ~ 1; 2; 3 HXDSP Eoo 4 OOTPUT Eoo 5 DElAY Eoo 6; 826C 8287 85F1 STATEJ£NT lEX TO DISPl.AY, SI)I( ~IT~ ROOTIt£ ;OOTPUT TO DISPI.AY, SI)I( ~IT~ ROOTII£ ;DElAY DISPI.
Temperature Sensor Code (Cont'd) ISIs- II 8888/8885 Ift:RO RSSEPllLER, Y2. 9 LOC OOJ 2829 CD6828 1:,1 SEQ 5(U(CE STATEIENT 53 ; 54 55; CALL fl>JUST ; caMRTS 8155 rom TO ~TlR. ~T 56; SETlf 57 .; II II :1 INITIILIZATI~ F~ SEARCH ROOTINE. ROOTINE LOOCS F~ TEIFERfITlRE RfNlE IF emn (SEE TEXT). SEARCH MV F~ Lfm< IR.F TO SIIRIFV COOE. 58; 282C 292E 2839 2831 2832 2834 2E88 2628 88 78 8E91 Cl>9228 I 59 68 61 ""I ""I L88H ~ 62 63 64 I«lY B A,B H,28H ; SET II. TO BEGII.
Temperature Sensor Code (Cont'd) ISIS-II 888eI8885 IflCRO ASSEIfIt.ER, V2. LOC r.eJ 2888 28IIA 298C 2eI:IE 2la lElll 0329 JEFF ()322 CF 2992 2992 BE 21193 DB 2894 23 21195 BE 21196 21197 2898 21199 2II9fI 2II9B 289C 2II9D 299E 2II9F 28A9 28A1 2IIR2 211Rl DB 23 BE DB 23 BE DB 23 BE DB 23 BE DB 23 2IIR4 BE 2IIR5 29A6 211R7 29A8 2fIA9 DS 23 BE DS 23 29ffi lID 28A9 C29228 2ft C9 20CE 29CE G1S29 2e..QlJ SEQ 1118 THIGH' 199 5(UC£ e IQ)llE PI&: STATE/DT ItVI A,93H em 28H A.
1 Temperature Sensor Code (Cont'd) ISIS-II 888818885 lIDO AS5eIl.ER, Y2.8 1,1 " LOC taJ SEQ SOJa STAIDENT 163 ; 164 2888 35 De 2881 36 2882 37 2883 38 I 2884 39 2885 3fI 2886 38 2887 3C 165 ; 166; sa=TWARE PW TO TElftRATlft 167 ; 168 II1G 28B8H 169 ; 178 ; 171 De 21H, 23H, 25ij, 2811, 31H, 35H, 39H I I 2888 " 2888 21 288C 23 2881) 25 288E 28 298F 31 2898 35 2991 39 172 ; 173 ; 174 IJ!(j 286eH 175 ; 176 .
CRT and Cassette Code PAGE LOC OeJ SEO A1-48 1
CRT and Cassette Code (Cont'd) ISIS- II 80:313/8118'5 ASSEMBLER. '"'1 0 :?e85 SEPIAL i/O 1·10r.E APPHIOI >:: lOC 08J PAGE 2 SOIJRCE STATEMHlT 1 2 .: :..' 4 .: 5 . S. ? : 8 : 9 : 1~~ THE FOLLO~~ING P~O(JRA~lS At-ID SUBROUTINES ARE DESCRIBED IN DETAIL IN HITEL CORPERATIOWS APPLICATION NOTE AP-29, "USING THE a0S5 SERlf'tI.. I/O LINES". THE FIF.:Si SECTION IS A GENERIiL PURPOSE CRT INTERFACE tHTH ~UTt)MATIC BAt!!) RATE WENTIFICATION.: THE ~.
CRT and !S!'~-II ·313S€l/:?0S5 ASSEMBLEP. Vi 31385 SEPIAl T/O NOTE HPPE~IDI:": I~ Ca~M,tte Code (Cont'd) MODl!Lg',i i::~;l: '~' ~; ":"" ' PAGE II I :~ I, LOC 08,.1 eS2F 87 ~81e F22708 138B E5 13814 24 1383:5 2C eS?6 22C829 0829 e8ZA 13838 eS3e 1383:[1 E1 B7 7C 1F SEa SOURCE STATEMENT !54 55 56 ORA A JP eRE 57 PIJSH 5e 59 69 £1 62 IHR 6:? ,'. I NOV PAl"' ; ~lO~l CORRESPON[iS TO INCOMING DATA RATE H : :':AVE COUNT FOP. HALFBIT TIriE COMPIJTATION H ; eITn~lE IS [iETEP.
CRT and Cassette Code (Cont'd) IS I 5-I I 8080/8085 ASSEMBLER, \/1, 8 8085 SERIAL I/O NOTE APPENDI:~ LO(: OB! eS77 eS7A e87B 087E 8a7F 98se C2760S 25 C2760S 7,7 79 1F 13881 0882 0SS? e886 98S7 B888 1.3889 4F as C26Fe8 E1 C1 FB C9 PAGE 1100ULE 4 SOURCE STATEMENT SEQ .INZ [iCP 102 le? 104 .
CRT and Cassette Code (Cont'd) ISIS-I I S0:?0/:::0:35 HSSE~lE:LEP,. 1.11 13 ::~)85 SERIAL I/O NOTE' APPENl'1:''': LOC PAGE CP;'F!TE EOU LEADEP EOU LC'F'C'Hf', EO!.! i2 : EUPCD "/ER~' LijNG TONE BUF.:ST ', TIMES THE ~'ltjPt'lAL 8URST [.'UF:AT!O~P TO ALLO~'1 RECOF.:DER ELECTRuNiCS fiNE, AGe TO STAE;ILIZE, THEN OUTPUTS THE REr'lAINDER OF HiE :::'56 F:'T'TE PAGE POWTED TO B'y' ':!-(:" STARTING AT 8'y'T£ (L), C, LF:A[)EP.: SET UP LEACH' BURST LPIGTH A. iX:€!H .; SET ACCUl'lfJl..
1 1 CRT and Cassette Code (Cont'd) ISIS-I I 8980.'OOSS ASSEMBLER. V1. 8985 SERIAL I/O HOTE APPENDJ:': 13 MOOULE PAGE ;; ~. :1. . LOC OSJ 08FF (:9 SEO SOURCE STATEMEm 2ea RET 2139 2113 .: PLAYBK ~JAITS FOR THE LONG LEADER BURST TO ARRIVE, THEN CONTINUES READING BYTES FROM THE RECORDER ANCo STORING THE~l 212 ; IN ~1Et~OPY STAIHINI3 AT LOCATION (HD. 213 .: CONTINUES UNTIL THE END OF THE CURRENT PAGE (L>=0FFH) IS REACHED. 214 PLAYBK' r~vI C' lDRCH~: .
CRT and Cassette Code (Cont'd) PAGE ISIS-II 913SI3,..'SOS5 RSSEJ'lEtEF.'., . .·'1 !J 8085 SEF'i~L !/Ct NOTE AF'PPIH:': LHP S'T'1'1BOLS Po !3??:F BIl A (i'?C? BR2 8URST Po \38FI~ (YRATE A (tfti6 ECHO A t3:3(1( PLA'.'Sr.· A IHel3 A 13919 TI2 8ITHI Po !)?::[:t E:Pll A 1)81F t1 138:3E CI'l A @86F COl HALJ:"81 A.2HCA A (l:?4A ':'1 t1 :~~1?2S TE PIE! BPI? 02 CO2 A !)(l09 A 1)::;:2::- A ';1896 A ~38;'t. HALFC'.
] ,I. CRT and Cassette Code (Cont'd) I I I ~' !SIS-! I ASSEHBLER 1?J1 24? erTIN 21S BITSr 16t BITS(l 1~t 8ITHM Btl a.rRcr! f' I; I 23:9 222 23'5 120 9S 60 100 129 165t1 167 1713* '1st F' 491 55 51 BIJ2 BURST ~r0t 28 2eu 2e1i1 Cll 165 12ft C12 125. C14 1291 Eet 127 en CIS C!N :e CfRATE 155t1 COl CO2 (OUT 97ft 42. 2137 2134 44 169 184 12? 126 142 El ... -!o 1"'" 200t 14lt HALFCY 1541 lDRCHr: 157ft LEADER 1561 PBl 21St 219. PB2 PlAYBK 214t 51 S1GNON 29 77.
I~ I~" I, II ,, I " I Ii I,
'I.
I i I' i '" I I,
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Introduction to Microprocessors Included in the price of the course is an SDK-8S kit which includes: 3 MHz 8085 CPU (enhanced 8080) Keyboard-24 keys Display-6 digits Monitor ROM 2048 bytes RAM Memory 256 bytes 381/0 Lines Teletype interface Complete documentation Course Description • Fundamental computer concepts and terminology introduced • Operation of the Intel 8085 microprocessor explained • 8085 assembly language programming • Stacks, subroutines, interrupts and I/O interfacing introduced • Lab sessio
MCS®-80/85 Microprocessors Course Outline DAY 1 Introduction to Microprocessors Assembly Language Instructions Programmed Input and Output Microcomputer Development System Monitor Lab: Using System Monitor DAY 2 Microcomputer Development System Disk Operating System CREDIT Text Editor and Macro Assembler The Processors Lab: Using Text Editor and Assembler DAY 3 Course Description Attendees • 8085 architecture explained in detail • Assembly language programming for 8080/8085 • Design and development of
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