User's Manual

x March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
B.4.1 Instruction Cache........................................................................................................... 17
B.4.1.1. Cache Miss Cost............................................................................................... 17
B.4.1.2. Round Robin Replacement Cache Policy......................................................... 17
B.4.1.3. Code Placement to Reduce Cache Misses ...................................................... 17
B.4.1.4. Locking Code into the Instruction Cache .......................................................... 18
B.4.2 Data and Mini Cache ..................................................................................................... 19
B.4.2.1. Non Cacheable Regions................................................................................... 19
B.4.2.2. Write-through and Write-back Cached Memory Regions ................................. 19
B.4.2.3. Read Allocate and Read-write Allocate Memory Regions ................................ 20
B.4.2.4. Creating On-chip RAM...................................................................................... 20
B.4.2.5. Mini-data Cache................................................................................................ 21
B.4.2.6. Data Alignment ................................................................................................. 22
B.4.2.7. Literal Pools ...................................................................................................... 23
B.4.3 Cache Considerations ................................................................................................... 24
B.4.3.1. Cache Conflicts, Pollution and Pressure .......................................................... 24
B.4.3.2. Memory Page Thrashing .................................................................................. 24
B.4.4 Prefetch Considerations ................................................................................................ 25
B.4.4.1. Prefetch Distances in the Intel
®
80200 Processor............................................ 25
B.4.4.2. Prefetch Loop Scheduling................................................................................. 27
B.4.4.3. Prefetch Loop Limitations ................................................................................. 27
B.4.4.4. Compute vs. Data Bus Bound .......................................................................... 27
B.4.4.5. Low Number of Iterations.................................................................................. 27
B.4.4.6. Bandwidth Limitations....................................................................................... 28
B.4.4.7. Cache Memory Considerations ........................................................................ 29
B.4.4.8. Cache Blocking................................................................................................. 31
B.4.4.9. Prefetch Unrolling ............................................................................................. 31
B.4.4.10.Pointer Prefetch .............................................................................................. 32
B.4.4.11.Loop Interchange ............................................................................................ 33
B.4.4.12.Loop Fusion .................................................................................................... 33
B.4.4.13.Prefetch to Reduce Register Pressure............................................................ 34
B.5 Instruction Scheduling ................................................................................................................ 35
B.5.1 Scheduling Loads .......................................................................................................... 35
B.5.1.1. Scheduling Load and Store Double (LDRD/STRD) .......................................... 37
B.5.1.2. Scheduling Load and Store Multiple (LDM/STM) ............................................. 38
B.5.2 Scheduling Data Processing Instructions ...................................................................... 39
B.5.3 Scheduling Multiply Instructions .................................................................................... 40
B.5.4 Scheduling SWP and SWPB Instructions...................................................................... 41
B.5.5 Scheduling the MRA and MAR Instructions (MRRC/MCRR)......................................... 42
B.5.6 Scheduling the MIA and MIAPH Instructions................................................................. 43
B.5.7 Scheduling MRS and MSR Instructions......................................................................... 44
B.5.8 Scheduling CP15 Coprocessor Instructions .................................................................. 44
B.6 Optimizing C Libraries ................................................................................................................ 45
B.7 Optimizations for Size................................................................................................................. 45
B.7.1 Space/Performance Trade Off....................................................................................... 45
B.7.1.1. Multiple Word Load and Store .......................................................................... 45
B.7.1.2. Use of Conditional Instructions ......................................................................... 45
B.7.1.3. Use of PLD Instructions .................................................................................... 45
C Test Features ............................................................................................ 1
C.1 Introduction................................................................................................................................... 1
C.2 JTAG - IEEE1149.1 ...................................................................................................................... 1
C.2.1 Boundary Scan Architecture ............................................................................................ 2