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Intel386™ OX MICROPROCESSOR HARDWARE REFERENCE MANUAL 1991
Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. Intel retains the right to make changes to these specifications at any time, without notice. Contact your local sales office to obtain the latest specifications before placing your order.
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PREFACE The Inte1386"1 DX microprocessor is a high-performance 32-bit microprocessor. This manual provides complete hardware reference information for Inte1386 DX microprocessor system designs. It is written for system engineers and hardware designers who understand the operating principles of microprocessors and microcomputer systems. Readers of this manual should be familiar with the information in the Introduction to the 80386 (Intel publication Order Number 231252).
PREFACE The Inte1386 SX processor (16-bit data bus) - The Intel386 DX processor adapted for mid-range personal computers, which are, sensitive to the higher system cost of a 32-bit bus. Related documentation includes: • 386™ SX Microprocessor Data Sheet, Order Number 240187 • 386™ SX Microprocessor Hardware Reference Manual, Order Number 240332 The 376 embedded processor (16-bit data bus) - A reduced form of the Intel386 processor, optimized for embedded applications.
PREFACE • Chapter 11, "Physical Design and Debugging." This chapter contains recommendations for constructing and debugging Intel386 DX microprocessor systems. • Chapter 12, "Test Capabilities." This chapter describes Intel386 DX microprocessor test procedures. • Appendix A contains descriptions of the components of the basic memory interface described in Chapter 6. • Appendix B contains descriptions of the components of the dynamic RAM subsystem described in Chapter 6.
TABLE OF CONTENTS CHAPTER 1 Page SYSTEM OVERVIEW 1.1 MICROPROCESSOR ...................................................................................................... 1-1 1.2 COPROCESSORS ............................................................................... '" ..... .... .... ... ........ 1-4 1.3 INTEGRATED SYSTEM PERIPHERAL ............................................................................ 1-4 1.4 CACHE CONTROLLER ..................................................... :..............
TABLE OF CONTENTS 3.6.1 HOLD/HLDA Timing ................................................................................................... 3.6.2 HOLD Signal Latency·............................................ .................................................... 3.6.3 HOLD State Pin Conditions ............................................ ...... .................. ................... 3.7 RESET .................................................................................................................
TABLE OF CONTENTS 6.3.5.1 DISTRIBUTED REFRESH ................................................................;...................... 6.3.5.2 BURST REFRESH ................................................................................................... 6.3.5.3 DMA REFRESH USING THE 82380 DRAM REFRESH CONTROLLER ................... 6.3.6 Initialization ................................................................. ............................................... Page 6-28 6-29 6-29 6-30 .
TABLE OF CONTENTS 8.5 BASIC I/O EXAMPLES .................................................................................................. 8.5.1 8274 Serial Controller ......... ;...................................................................................... 8.5.2 82380 Programmable Interrupt Controller ................................................................ 8.5.2.1 CASCADED INTERRUPT CONTROLLERS TO THE 82380 PIC ............................ 8.5.3 8259A Interrupt Controller ...............
TABLE OF CONTENTS Page CHAPTER 11 PHYSICAL DESIGN AND DEBUGGING 11.1 GENERAL DESIGN GUIDELINES ............................................................................... 11-1 11.2 POWER DISSIPATION AND DISTRIBUTION .............................................................. 11-1 11.2.1 Power and Ground Planes .......... ............ .... ........ ................................. ................ .... 11-2 11.3 DECOUPLING CAPACITORS ..................................................................
TABLE OF CONTENTS Figures Figure 1-1 , 1-2 2-1 2-2 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 5-1 5-2 r 5-3 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 Title Page Intel386™ DX Microprocessor System Block Diagram ................................. . Micro Channel-Compatible Solution with 82311 Chip Set ........................... . Instruction Pipelining ...............................
TABLE OF CONTENTS Figures Figure 7-15 7-16 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9' 8-10 8-11 8-12 8-13 8-14 8-15 8-16 8-17 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 10-1 10-2 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 11-16 11-17 11-18 11-19 11-20 11-21 11-22 Title Page Two-Way Set Associative Cache without Data Buffers ................................. . Two-Way Set Associative Cache with Data Buffers ...................................... .
in.teI® TABLE OF CONTENTS Figures Figure Title Page 11-23 11-24 11-25 11-26 11-27 11-28 11-29 11-30 12-1 12-2 A-1 A-2 A-3 B-1 B-2 B-3 B-4 Closed Loop Signal Paths are Undesirable ................................................. .. Typical Intel386™ OX Microprocessor Clock Circuit ..................................... . CLK2 Timing Diagram ................................................................................... . Clock Routing ........ :......................................................
System Overview 1
CHAPTER 1 SYSTEM OVERVIEW The Intel386 DX microprocessor is a 32-bit microprocessor that forms the basis for a high-performance 32-bit system. The Inte1386 DX microprocessor incorporates multitasking support, memory management, pipelined architecture, address translation caches, and a high-speed bus interface all on one chip. The integration of these features speeds the execution of instructions and reduces overall chip count for a system.
SYSTEM OVERVIEW CLOCK GENERATOR CLK2 1386" OX MICRO· PROCESSOR 1387'· OX MATH COPROCESSOR CACHE MEMORY 82835 CACHE CONTROLLER MAIN MEMORY 82370 OMA 82596 OX LAN COPROCESSOR PERIPHERALS 231732i1-1 Figure 1-1. l"ntel386™ OX Microprocessor System Block Diagram in detail in Chapter 2.
SYSTEM OVERVIEW r:=:J INDICATES CHIP SET 231732i1-2 Figure 1-2. Micro Channel-Compatible Solution with 82311 Chip Set The integrated memory management and protection mechanism translates logical addresses to physical addresses and enforces the protection rules necessary for maintaining task integrity in a multitasking environment. The paging function simplifies the operating-system swapping algorithms by providing a uniform mechanism for managing the physical structure of memory.
SYSTEM OVERVIEW Table 1-1.
SYSTEM OVERVIEW The 82380 Integrated System Peripheral is a multi-function Intel386 DX microprocessor companion chip. It integrates a 32-bit DMA Controller with other necessary processor support functions needed in an Intel386 DX microprocessor environment. The 82380 is optimized for use with the Intel386 DX microprocessor. It enhances the overall Intel386 DX microprocessor system performance by providing high data throughput as well as efficient bus operation.
SYSTEM OVERVIEW The 82385 Cache Controller is a high performance peripheral designed specifically for . the Intel386 DX microprocessor. The 82385 allows the Intel386 DX microprocessor to reach its full performance potential by offering the following features: • Supports a 32-kbyte cache memory organized as either 2-way set associative or direct mapped. • Integrated cache directory and management logic. • Utilizes posted writes for zero wait states on write cycles.
SYSTEM OVERVIEW • • • • 82308 82309 82706 82077 Micro Channel Bus Controller Address Bus Controller VGA Graphics Controller Floppy Disk Controller The 82311 solution not only offers Micro Channel compatibility, but also high integration and performance. It features all the peripheral functions required to interface to the CPU, Micro Channel Bus, I/O Peripheral Bus and the Graphics Channel. The 82311 chip set supports the Inte1386 DX microprocessors up to 25 MHz, and the . Inte1386 SX microprocessor. 1.
SYSTEM OVERVIEW The 8259A Programmable Interrupt Controller manages interrupts for an Inte1386 DX microprocessor system. Interrupts from as many as eight external sources are accepted by one 8259A; as many as 64 requests can be accommodated by cascading several 8259A chips. The 8259A resolves priority between active interrupts, then interrupts the processor and passes a code to the processor to identify the interrupting source.
Internal Architecture 2
CHAPTER 2 I NTERNAL ARCHITECTURE The internal architecture of the Intel386 DX microprocessor consis~s of six functional units that operate in parallel. Fetching, decoding, execution, memory management, and bus accesses for several instructions are performed simultaneously. This parallel operation is called pipelined instruction processing. With pipelining, each instruction is performed in stages, and the processing of several instructions at different stages may overlap as illustrated in Figure 2-1.
INTERNAL ARCHITECTURE The Execution Unit in turn consists of three subunits: • Control Unit • Data Unit • Protection Test Unit Figure 2-2 shows the organization of these units. This chapter describes the function of each unit, as well as interactions between units. 2.1 BUS INTERFACE UNIT The Bus Interface Unit provides the interface between the Inte1386 DX microprocessor and its environment.
l SEGMENTATION UNIT ; ~~~gR~N~MI 3-INPUT ADDER 32 EFFECTIVE ADDRESS BUS PAGING UNIT i i EFFECTIVE ADDRESS BUS JI D~SCRIPTION REGISTERS / RESET. HLDA PAGE CACHE ...I ~ 32 EXECUTION UNIT --l 1-- ? ----::::-1 I I L-,.-,-_",-' 8 LIMIT AND ATTRIBUTE PLA Z -I m BEO# - BE3# I A2-A31 ::D M/IOH. D/CH. .-» z I I I ....-----,==~ L--r'"'-=="--~=~ » W/RH. LOCKH. I L __ I\) CiJ ADSH. NAH. READYH BSI6#. READY# ::D n ::I: =i DO-D31 I I BARREL SHIFTER.
INTERNAL ARCHITECTURE 2.4 EXECUTION UNIT The Execution Unit executes the instructions from the Instruction Queue and therefore communicates with all other units required to complete the instruction. The functions of its three subunits are as follows: • The Control Unit contains microcode and special parallel hardware that speeds mul~ tiply, divide, and effective address calculation.
Local Bus Interface 3
CHAPTER 3 LOCAL BUS INTERFACE Local bus operations are considered in this chapter. The Inte1386 DX microprocessor performs a variety of bus operations in response to internal conditions and external conditions (interrupt servicing, for example). The function and timing of the signals that make up the local bus interface are described, as well as the sequences of particular local bus operations. The high-speed bus interface of the Intel386 DX microprocessor provides high performance in any system.
LOCAL BUS INTERFAcE • The CLK2 input provides a double-frequency clock signal for synchronous operation. This signal is divided by two internally, so the Intel386 DX microprocessor fundamental frequency is half the CLK2 signal frequency. For example, a 20-MHz Intel386 DX microprocessor uses a 40-MHz CLK2 signal. • The RESET input forces the Intel386 DX microprocessor to a known reset state.
LOCAL BUS INTERFACE Table 3-1.
lOCAL BUS INTERFACE Table 3-2.
LOCAL BUS INTERFACE Each bus cycle is comprised of at least two bus states, Tl and T2. Each bus state in turn consists of two CLK2 cycles, which can be thought of as Phase 1 and Phase 2 of the bus state. Figure 3-2 shows bus states for some typical read and write cycles. During the first bus state (Tl), address and bus status pins go active. During the second bus state (T2), external logic and devices respond.
LOCAL BUS INTERFACE ALWAYS READY# ASSERTED· REQUEST PENDING BUB READY# NEGATED· NA# NEGATED States: T1-first clock of a non-pipelined bus cycle (80386 drives new address and asserts ADS") T2-subsequent clocks of a bus cycle when NA" has not been sampled asserted in the current bus cycle H- idle state The fastest bus cycle consists of two states: T1 and T2. 231732i3-3 Figure 3-3. Bus State Diagram (Does Not Include Address Pipelining) 3.1.
LOCAL BUS INTERFACE n NON·PIPELINED n n ~ n .' I.. .' 1.2 .' I.. .' I.. .' I .. CLK2 (INPUT) BEOII-BE3', A2-A31, MIIOM, D/C', WfRlt (OUTPUTS) ADS' (OUTPUT) NA' (INPUT) READYiI (INPUT) LOCKt (OUTPUT) DO-D31 (INPUT DURING READ) PIPELINED CLK2 (INPUT) BEDN-BE3#,A2-A31, M/IO#, DIe", W/R,. (OUTPUTS) ADSit (OUTPUT) NM (INPUT) READY' (INPUT) LOCK" (OUTPUT) Do-D31 (INPUT DURING READ) 231732i3-4 Figure 3-4.
LOCAL BUS INTERFACE The programmer views the address space (memory or I/O) of the Intel386 DX microprocessor as a sequence of bytes. Words consist of two consecutive bytes, and double words consist of four consecutive bytes. However, in the system hardware, address space is implemented in four sections. Each of the four 8-bit portions of the data bus (DO-D7, D8-DIS, DI6-D23, and D24-D31) connects to a section. When the Intel386 DX microprocessor reads a doubleword, it accesses one byte from each section.
LOCAL BUS INTERFACE BYTE ADDRESS WORD ADDRESS DWORD ADDRESS 0 1 2 0 0 2 2 0 0 0 0 BEO BEl BE2 BE3 3 BEO 4 4 4 BEl 5 4 4 BE2 6 7 4 8 6 6 8 - - - BE3 BEO 4 8 - - - - - - 131 24123 BE3# 81 7 16115 BE2# BE1# BEO# 01 231732i3-6 Figure 3-6. Address, Data Bus, and Byte Enables for 32-Bit Bus Table 3-3.
LOCAL BUS INTERFACE Figure 3-7 shows the steps required for a misaligned 32-bit transfer. In the first bus cycle, the physical address crosses over into the next doubleword location, and BEO# and BEl # are active. In the second bus cycle, the address is decremented to the previous doubleword, and BE2# and BE3# are active. After the transfer, the data bits are automatically assembled in the correct order. Table 3-4 shows the sequence of bus cycles for all possible misaligned· transfers.
LOCAL BUS INTERFACE Table 3-4. Misaligned Data Transfers on 32-Bit Bus First Cycle Transfer Type Physical Address Word 4N Doubleword 4N Doubleword 4N Doubleword 4N + + + + Byte Enables Address Bus Byte Enables 4 0 4N 3 4 0 4N 1-3 4 0-1 4N 2-3 4 0-2 4N 3 Address Bus 3 4N 1 4N 2 4N 3 4N + + + + Second Cycle Because the Intel386 DX microprocessor operates on only bytes, words, and doublewords, certain combinations of BE3#-BEO# are never produced.
LOCAL BUS INTERFACE IDLE TI CYCLE 2 NON·PIPElINED (READ) CYCLE 1 NON·PIPELINED (READ) T1 T1 T2 T2 IDLE n T2 ClK2 ClK BEO#-BE3#, A2-A31, M/IO#, DIC# W/R# AD5# NA# B516# READY# VALID 2 lOCK# DO-D31 - --- --,- --0-- - I 231732i3·8 Figure 3-8. Non-Pipelined Address Read Cycles • At the end of T2, READY# is sampled. If READY# is low, the Inte1386 DX microprocessor reads the input data on the data bus.
LOCAL BUS INTERFACE 3.1.5 Write Cycle Write cycles, like read cycles, are of two types: pipelined address and non-pipelined address. Pipelined address cycles are described in Section 3.1.6. Figure 3-9 shows two non-pipelined address write cycles (one with and one without a wait state. The sequence of, signals for a non-pipelined write cycle is as follows: • The Intel386 DX microprocessor initiates the cycle by driving ADS# low.
LOCAL BUS INTERFACE Ti T1 IDLE CYClE2 NON·PIPElINEO (WRITE) CYCLE 1 NON·PIPELINEO (WRITE) T1 T2 T2 T2 Ti ClK2 ClK BEO#·BE3# A2-A31, M/IO#,O/C# W/R# AOS# NA# BS16# REAOY# lOCK# 00-031 231732i3-9 Figure 3-9. Non-Pipelined Address Write Cycles Figure 3-10 illustrates the effect of NA#. During the second eLK cycle (T2) of a nonpipelined address cycle, NA# is sampled low.
LOCAL BUS INTERFACE IDLE n CYCLE 2 NON-PIPELINED (READ) CYCLE 1 NON-PIPELINED (WRITE) T1 T2 T1 T2 T2P CYCLE 3 PIPELINED (WRITE) T1 P T2P CYCLE ~ PIPELINED (READ) T1 P T21 IDLE n CLK2 [ CLK [ 8EO# - 8E3# [ A2-A31. W/IO#.D/C# W/R# [ ADS# [ NA# [ 8516# [ READY# [ LOCK # [ £¥~t:::£.~~M?'~~>C::l.~ C¥~c.!.~~~~-+~~~'" "'~~r'-......;;;;:;;:....:.....-r'--+-----r '---:----r '-.......;~---f\j~~ 00- 031 [ Following any idle bus state (Ti), addresses are non-pipelined.
LOCAL BUS INTERFACE Once NA# is sampled active, it remains active internally throughout the current bus cycle. If NA# and READY # are active in the same CLK cycle, the state of NA# is irrelevant, because READY # causes the start of a new bus cycle; therefore, the new address and status signals are always output regardless of the state of NA#. A complete discussion of the considerations for using address pipelining can be found in the 386'" DX Microprocessor Data Sheet (Order Number 231630). 3.1.
LOCAL BUS INTERFACE PREVIOUS CYCLE T2 ClK2 [ ClK [ BEl #. BE2#. BE3# [ BEO#. A3-A31. [ M/IO#. D/C#. W/R# I INTERRUPT ACKNOWLEDGE CYCLE I T1 T2 IDLE (4 BUS STATES) T2 TI TI Ti INTERRUPT ACKNOWLEDGE CYCLE 2 I Tl 11 T2 IOLE n T21 JUl rut rut rul rut rut rut illh.Il rut rul n.n. -V V V V V V V V V V V V .... ~ ,Jf\Jf\ ,Jf\X XX X r ... "'V'ir" lXX)! XXX)! .Jf\Jf\ .1'1. ",...&...., ,X ,X XX /" X ~XX ,/ lOCK# [ ADS# [ 00-07 [ 08-031 [ .(OJ. .1'1.
LOCAL BUS INTERFACE As with other bus cycles, a halt or shutdown cycle is initiated by activating ADS# and the bus status pins as follows: • M/IO# and W/R# are driven high, and D/C# is driven low to indicate a halt or shutdown cycle. • All address bus outputs are driven low. For a halt condition, BE2# is active; for a shutdown condition, BEO# is active. These signals are used by external devices to respond to the halt or shutdown cycle. READY # must be asserted to complete the halt or shutdown cycle.
LOCAL BUS INTERFACE the bus before the end of the current bus cycle. Therefore, because both signals are sampled at the same sampling window, BSI6# must be active before or at the same time as NA# to guarantee 16-bit operation. Once NA# is sampled active in a bus cycle and BSI6# is not active at that time, BSI6# must be negated for the remainder of the bus cycle.
LOCAL BUS INTERFACE A TRANSFER REQUIRING TWO CYCLES ON 16·BIT DATA BUS IDLE I TI IDLE CVCLE1 NON·PIPELINED (WRITE) T1 T2 TI CLK2 CLK2 CLK CLK BEO#-BE3#, A2-A31, MIIO#, D/C# BEO#, BE1# WIR# CVCLE1A NON·PIPELINEO WRITE) PART TWO T1 T2 CVCLE1 NON·PIPELINED (WRITE PART ONE T1 I T2 CJpL.l£lUt"'----I-~ BE2#, BE3#, A2-A31 , ~JVq MIIO#, OIC# nb~-,j,V"--i---i---i--""i .ajC:J.~I£lI'\.--+---+---+---f AOS# AOS# BS16# ~£.lllp~ B516# 00-015 231732i3-13 Figure 3-13.
LOCAL BUS INTERFACE 32 DATA BUS (00-031) 1386'· OX ADDRESS BUS (BEO#-BE3#.A2-A31) CPU 32-BIT I.lEI.lORY TBS16# "HIGH" 32 DATA BUS (00-D31) ADDRESS BUS (BEO#-BE3#, A2-A31) 16 DATA BUS (00-DI5) 231732;3-14 Figure 3-14. 32-Bit .and 16-Bit Data Addressing • If BEO# and BEI# are both inactive during a BSl6 cycle, and either BE2# or BE3# is active, For a write cycle, data on D31-D16is duplicated on DIS-DO, regardless of the state of BSI6#.
LOCALBU51NTERFACE Table 3-S.
lOCAL BUS INTERFACE 3.2 BUS TIMING This section describes timing requirements for read cycles, write cycles, and the READY# signal. All Inte1386 DX microprocessor signals have setup and hold time requirements relative to CLK2. The timings of certain signals relative to one another depends on whether address pipelining is used. These facts must be considered when determining external logic needed to facilitate bus cycles.
LOCAL BUS INTERFACE The minimum amount of time from the output of valid write data by the access device to the end of the write cycle is the least amount of time external logic has to read the data. This setup time is Three CLK2 cycles (at 20 MHz) - D31-DO output delay (maximum) 75 nanoseconds - 38 nanoseconds 37 nanoseconds (With N wait states) (+ N*50 nanoseconds) Data outputs are valid beyond the end of the bus cycle.
lOCAL BUS INTERFACE 3.3 CLOCK GENERATION 3.3.1 Clock Timing The CLK2 and CLK outputs of the clock generator are both MOS-Ievel outputs with output high voltage levels of Vcc-0.6V and adequate drive for TTL inputs.CLK2 is twice the frequency of CLK. The internal CLK signal of the Intel386 DX microprocessor is matched to the external CLK output by the falling edge of the RESET signal. This operation is described with the RESET function in Section 3.7.
LOCAL BUS INTERFACE 3.3.2 Crystal Oscillator Clock Generator Figure 3-16 shows a clock generator circuit for the Intel386 DX microprocessor. It is implemented with TTL and CMOS components. It provides the CLK2, CLK, and RESET signals needed by the Intel386 DX microprocessor and local bus controller. The CLK2 signal provides the fundamental timing for the Intel386 DX microprocessor and is generated by a CMOS crystal oscillator.
LOCAL BUS INTERFACE 74F109 11 14 J ADS PR 10 QI--'---I 12 CK 13 K Q ADSO 9 15 ClK 10NS 231732i3-17 Figure 3-17. ADS# Synchronizer An alternative method of generating CLK2 is to use a TTL oscillator coupled to a 74ACT244 buffer.
LOCAL BUS INTERFACE depends on the type of interrupt; if the interrupt is maskable (INTR input active), the vector is supplied by the 8259A Interrupt Controller. If the interrupt is nonmaskable (NMI input active), location 2 in the IDT is used automatically. The NMI request and the INTR request differ in that the Intel386 DX microprocessor can be programmed to ignore INTR requests (by clearing the interrupt flag of the Intel386 DX microprocessor).
LOCAL BUS INTERFACE An NMI request automatically causes the Inte1386 DX microprocessor to execute the service routine corresponding to location 2 in the IDT. The Intel386 DX microprocessor will not service subsequent NMI requests until the current request has been serviced. The Inte1386 DX microprocessor disables INTR requests (although these can be reenabled in the service routine) in Real Mode. In Protected Mode, the disabling of INTR requests depends on the gate in IDT location 2. 3.4.
LOCAL BUS INTERFACE • Saving the Flags register and CS:EIP registers (which contain the return address) requires time. • If interrupt servicing requires a task switch, time must· be allowed for saving and restoring registers. • If the interrupt service routine saves registers that are not automatically saved by the Intel386 DX microprocessor, these instructions also delay the beginning of interrupt servicing.
LOCAL BUS INTERFACE SEMAPHORE BUS MASTER 1 READS VALUE 0 = NOT BUSY BUS MASTER 1 WRITES VALUE 1 = BUSY -EJj LOCKED CYCLES -8 BUS MASTER 2 READS VALUE 1 = BUSY BUS MASTER 1 HAS CONTROL OF DEVICE BUS MASTER 2 WAITS FOR VALUE TO CHANGE NO ERROR SEMAPHORE r::1 BUS MASTER 1 READS VALUE O=NOT BUSY -~ / / UNLOCKED CYCLES r;;1_ / \ L.
LOCAL BUS INTERFACE UNLOCKED BUS CYCLE lOCKED lOCKED BUS CYCLE BUS CYCLE UNLOCKED BUS CYCLE ClK BE3#-BEO# A31-A2 lOCK# NA# READY# 231732i3-19 Figure 3-19. LOCK# Signal during Address Pipelining 3.5.3 LOCK# Signal Duration The maximum duration of the LOCK# signal affects the maximum HOLD request latency because HOLD is not recognized until LOCK# goes inactive. The duration of LOCK# depends on the instruction being executed and the number of wait states per cycle.
LOCAL BUS INTERFACE 3.6.1 HOLD/HLDA Timing To gain control of the local bus, the requesting bus master drives the Inte1386 DX microprocessor HOLD input active. This signal must be synchronous to the CLK2 input of the Inte1386 DX microprocessor. The Inte1386 DX microprocessor responds by completing its current bus cycle (plus a second locked cycle or a second cycle required by BS16#).
LOCAL BUS INTERFACE HOLD .... SSERTED READY" ASSERTEDHOLD NEGATEO- NO REOUEST Bus States: T1-fjrst clock of a non·pipelined bus cycle (80386 drives new address 811d ' asserts ADS #). T2-subsequenl clocks of a bus cycle when NA # has not been sampled asserted in the current bus cycle. T21-subsequent clocks of a bus cycle when NA # has been sampled asserted in the current bus cycle but there is not yet an internal bus request pending (80386 will not drive new address or assert ADS #).
LOCAL BUS INTERFACE 3.6.3 HOLD State Pin Conditions LOCK#, M/IO#, D/C#, W/R#, ADS#, A31-A2, BE3#-BEO#, and D31-DO enter the three-state OFF condition in the HOLD state. Note that external pullup resistors may be required on ADS#, LOCK# and other signals to guarantee that they remain inactive during transitions between bus masters. 3.7 RESET RESET starts or restarts the Inte1386 DX microprocessor. When the Intel386 DX microprocessor detects a low-to-high transition on RESET, it terminates all activities.
lOCAL BUS INTERFACE CLK2 [ RES# [~'----------5S 5 mml THE CLOCK GENERATOR ENSURES THAT ITS RESET OUTPUT FALLING EDGE OCCURS DURING PHASE lWO RESET [ _ _ _ _--1/,.-------SS 5-5- - - - - -.....{'--_ _ _ __ 1386 N ox CPU ASSUMES RESET FALLING EDGE OCCURS DURING PHASE lWO, AND SETS ITS OWN INTERNAL PHASE TO MATCH 231732i3-21 Figure 3-21.
Performance Considerations 4
CHAPTER 4 PERFORMANCE CONSIDERATIONS System performance measures how fast a microprocessing system performs a given task or set of instructions. Through increased processing speed and data throughput, a Inte1386 DX microprocessor operating at the heart of a system can improve overall performance immensely. The design of supporting logic and devices for efficient interaction with the Intel386 DX microprocessor is also important in optimizing system performance.
PERFORMANCE CONSIDERATIONS Table 4-1. Intel386™ DX Microprocessor Performance with Wait States and Pipelining Wait States When Address is Pipelined Wait States When Address is Not Pipelined Performance Relative to Non-Pipelined o Wait-State Bus Utilization 0 0 1.00 73% 0 1 0.91 79% 1 1 0.81 86% 1 2 0.76 89% 2 2 0.66 91% 2 3 0.63 92% 3 3 0.57 93% states without address pipelining would require one wait state with address pipelining.
PERFORMANCE CONSIDERATIONS Consider a system in which a non-pipelined memory access requires one wait state and a non-pipelined I/O access requires four wait states. The bus control logic reads chip select signals from the address decoder to determine whether one or four wait states are required for the bus cycle. The bus control logic also determines whether the address has been pipelined, because a pipelined cycle requires one less wait state.
Coprocessor Hardware Interface 5
CHAPTER 5 COPROCESSOR HARDWARE INTERFACE A numeric coprocessor enhances the performance of an Inte1386 DX microprocessor system by performing numeric instructions in parallel with the Inte1386 DX microprocessor. The Inte1386 DX microprocessor automatically passes on these instructions to the coprocessor as it encounters them. The Intel387 DX math coprocessor performs 32-bit data transfers and interfaces directly with the Intel386 DX microprocessor.
COPROCESSOR HARDWARE INTERFACE • ERROR# is asserted after a coprocessor math instruction results in an error that is not masked by the coprocessor's control register. The data sheets for the Intel387 DX math coprocessor describe these errors and explain how to mask them under program control. If an error occurs, ERROR# goes active before BUSY # goes inactive, so that the Intel386 DX microprocessor can take care of the error before performing another data transfer. 5.
COPROCESSOR HARDWARE INTERFACE FROM OTHER PERIPHERALS ADSO# ~>- • ri387'" OX NPX CLOCK GENERATOR (OPTIONAL) CLOCK GENERATOR CLK2 ClK ..... CKM 387CLK2 386ClK2 RESET IN RESET READY# ADS# WAIT STATE GENERATOR (OPTIONAL) AND OR lOGIC -------- ~ i..-...-....., -- t i387'" OX lOCK# READY# BEO#-BE3# CLK2 MIIO# BS16# A31 NA# HOLD INTR NMI A30-A3 1386'" OX READYO# MATH COPROCESSOR HLDA DIC# RESET - A2 :.....-. :.....-.
COPROCESSOR HARDWARE INTERFACE • The Intel387 DX math coprocessor READY#, ADS#, and W/R# inputs are connected. to the corresponding pins on the Intel386 DX microprocessor. READY # and ADS# are used by the Inte1387 DX math coprocessor to track bus activity and determine when W/R#, NPS1#, NPS2, and Status Enable (STEN) can be sampled. • Status Enable (STEN) serves as a chip select for the Inte1387 DX math coprocessor.
COPROCESSOR HARDWARE INTERFACE • In pseudo-synchronous mode, CKM is low and a frequency source for the 387CLK2 input must be provided. Only the interface logic of the Intel387 DX math coprocessor is synchronous with the Inte1386 DX microprocessor. The internal logic of the Intel387 DX math coprocessor operates from the 387CLK2 clock source, whose frequency may be 10/16 to 14/10 times the speed of CLK2. Figure 5-2 depicts pseudosynchronous operation. 5.
COPROCESSOR HARDWARE INTERFACE Two, three, four or five bus cycles may be necessary for each operand transfer. These cycles include one coprocessor cycle plus one of the following: • • • • One memory cycle for an aligned operand Two memory cycles for a misaligned operand Two Or three memory cycles for misaligned 32-bit operands to 16-bit memory Four memory cycles for misaligned 64-bit operands to 16-bit memory Data transfers for the coprocessor have the same bus priority as programmed data transfers. 5.
COPROCESSOR HARDWARE INTERFACE ~B~b/67/~~/lab MACRO ASSEMBLER PAGE 1 Test for presence of a Numerics Chip. Revision 1." DOS 3.2B (B33-Nl aB~b/671a6/16b MACRO ASSEMBLER V2.B ASSEMBLY Of MODULE TEST- NPX OBJECT MODULE PLACED IN fINDNPX.oBJ LaC OBJ LINE SOURCE +1 StitleC'Test for presence of a Numerics Chip. Revision 1.
COPROCESSOR .HARDWARE INTERFACE 606b/a7/6MlSb MACRO ASSEMBLER Test for presence of a Numerics Chip, Revision 1.0 LOC OBJ SOURCE 001F 0022 0025 0026 002B 002E 0031 'BD'Ea 'BD'EE 'BDEF' 'BD'C0 'BD'E0 'BDED' 'BDD3C LINE 003~ 6B0~ 003b 'E 0037 7~0b ~, 5~ 55 5b 57 56 5' fstsw {sO· lIIav ax,[siJ sahf je found_a7_2a7 See if the infinities matched Jump if a0a7l287 is present An i367 SX/DX NPX is present', If denormal exceptions are used for an 6B.!.71267, they must be masked.
Memory Interfacing , 6
CHAPTER 6 MEMORY INTERFACING The Intel386 DX microprocessor high-speed bus interface has many features that contribute to high-performance memory interfaces. This chapter outlines approaches to designing memory systems that utilize these features, describes memory design considerations, and lists a number of useful examples. The concepts illustrated by these examples apply to a wide variety of memory system implementations. 6.
MEMORY INTERFACING The block diagram of the basic memory interface is shown in Figure 6-1. The bus control logic provides the control signals for the address latches, data buffers, and memory devices; it also returns READY # active to end the Intel386 DX microprocessor bus cycle and NA# to control address pipelining. The address decoder generates chip-select signals and the BS16# signal based on the address outputs of the Intel386 DX microprocessor.
MEMORY INTERFACING Table 6-1. Common Logic Families* 74xxx The original TIL family. Now obsolete. 74Lxxx Low-power version of standard TTL. Very slow and now obsolete. 74LSxxx Low-power Schottky TIL. Lower power and higher speed than standard TIL. Widely used in microprocessor systems. 74Sxxx Schottky TIL. High speed and high power consumption. Now obsoleted by newer families. 74ALSxxx Advanced low-powe'r Schottky TIL.
MEMORY INTERFACING EPLDs have the following additional advantages: 1. Programmability/erasability allows EPLD functions to be changed easily, simplifying prototype development. 2. Since EPLDs are implemented in CMOS technology, they can consume an order of magnitude less power than bipolar PLDs. Power-conscious applications can benefit greatly from using EPLDs. 3.
i: @l BOOLEAN EQUATION: D=A"Q"/B +/A " IQ • B; EPLD IMPLEMENTATION: CLK ..... IA A IS S IB B OE s: s: m =8= -g- olJ -< -Q-~ O'l g: &, CLK ~ I/O r±JD COMBINATIONAL OR REGISTERED (SELECTABLE) S FROMB INPUT 231732;6·2 Figure 6-2.
MEMORY INTERFACING OE 1/0 PIN o Q I I ClK INVERT CONTROL I I I MACROCEll REGISTER I I I I I I I FEEOBACK II SELECT: IL________________ I ~ 231732i6-3 Figure 6-3. 85C220 EPLD Macrocell Architecture PLDs and other Programmable Logic Devices are specified by part number. Different manufacturers use different numbering schemes. Intel PLDs are described in the Programmable Logic Handbook.
MEMORY INTERFACING along with the address. Therefore, the number of address latches needed is determined by the location of the address decoder as well as the number of address bits and chipselect signals required by the interface. Chip-select signals can be routed to the bus control logic to set the correct number of wait states for the accessed device. The decoder consists of two one-of-four decoders, one for memory address decoding and one for I/O address decoding.
l 85C220 CLOCK & INT "ESET GENERATOR CLK RESET CLK2 I RESET T CLK2 ~ - - IOPLD1 8259A CLK2 CLK NA _lORD ~"DY~ - IOPLD2 CLK2 - TRtOEN - WICNTO CLK ADS WTCHT' READY WTCNT2 M/IO# MIlO W/R# WI" INTA INTA D/C D/C EPRD EPRDY A3.
MEMORY INTERFACING The bus controller decodes the Inte1386 DX microprocessor status outputs (W/R#, M/IO#, and D/C#) and activates a command signal for the type of bus cycle requested. The command signal corresponds to the bus cycle types (described in Chapter 3) as follows: • Memory data read and memory code read cycles generate the EPROM Read Command (EPRD#) output. EPRD# commands the selected memory device to output data. • I/O read cycles generate the I/O Read Command (IORD#) output.
l EPROM READ NON-PIPELINED EPROM nlT2IT2!T21T2 IIDLElnlT2 READ nln T112 I NON-PIPEUNED T2JT2 T2 11 I T. I T2 I T2 I T2 I @J T2 CLK' PCLK ADS# ADDR ALEIO ~ ~.- s: s: ~ m EPRD# \ TIMEDLY ~ ~ . _ - - - / / \ TRIOEN \ o \ / o / \ ~ Z / \ / -I m :JJ DT_R~ DATA READ READ ~ Q z ) NA# B516# BUSCYC IQRDY# \ \ / ~ f\ '----./. C> / 1\'---_ _ ~ 231732i6-5 Figure 6-5.
MEMORY INTERFACING tRR: Read (EPRD#) pulse width (10 x CLK2 period) (10 x 25) - PLD RegOut Skew (EPRD# low to high) - 4 = 246 nanoseconds tRA: Address hold after Read (EPRD# rise) + PLD RegOut Min (0 x CLK2 period) - PLD RegOut Max (EPRD#) (ALEIO) + Latch Enable Min (0 x 25) - 6 + 2 + 5 1 nanoseconds tAD: Data delay from Address (12 x CLK2 period) - xcvr. prop.
MEMORY INTERFACING EPROMs only for power-on initialization and runs programs entirely from SRAM or DRAM has only a power-on time increase over the 32-bit EPROM system; its main programs run at the same speed as the 32-bit system. The Intel386 DX microprocessor BS16# input directs the Intel386 DX microprocessor to perform data transfers on only the lower 16 bits of the data bus. In systems in which 16-bit memories are used, the address decoder logic must generate the BS16# signal for 16-bit accesses.
MEMORY INTERFACING Even if random accesses are made, two DRAM banks allow 50 percent of back-to-back accesses to be made without waiting for the DRAMs to precharge. The precharge time is also avoided when the Intel386 DX microprocessor has no bus accesses to be performed. During these idle bus cycles, the most recently accessed DRAM bank can precharge so that the next memory access to either bank can begin immediately. The DRAM memory system design described here uses two interleaved banks of DRAMs.
MEMORY INTERFACING The number of wait states for same-bank accesses applies only to back-to-back cycles (without intervening idle bus time) to the same bank of DRAMs. Because the controller must allow the DRAMs to precharge before starting the access, address pipelining does not speed up the same-bank cycle; the number of wait states is identical with or without address pipelining. The numbers in Table 6-2 are affected by DRAM refresh cycles.
l CLK2 PCLK" DRAIIP2 WE RASO ...,220 CR RAS1 RAS1P DAAMSTART RASOP MUXOE' WIR ~ i II REF", CAS REFREC RESET ALE DRAMRDY W/A#I BANK 0 ~ ~56 CAS# X8 ~ WEO 25. X8 ~C:~O "0 w_-'-".. CAS# 1386'· OX CPU ~ I I CAS# RAS# DRAMPl PAZ P2M8ROWSEL r-l>-I-++I-+-f IREADY C11 I I WEO ~----------+-----+-~+1~MIO READY# RASO RAS1P RAS1 REFIN A12-A20 - c g ~ .....J!W WEO CAS# DRAMSTART :: =~~~ 25.
MEMORY INTERFACING the RAS# from that bank and BEO# with the CAS# signal to enable the leastsignificant byte (D7-DO). Similarly, CAS3# is generated by RAS#, BE3# and CAS# and enables the most significant byte (D31-D24). The Write Enable (WE#) and the multiplexed address signals are connected to every DRAM module in both banks. For drive considerations the multiplexed address is generated separately for each bank.
MEMORY INTERFACING Provides the data transceiver and address latch control signals Produces the CAS# and WE# DRAM signals Generates the READY# signal to end DRAM bus cycles A DRAM read or write access is requested when all the chip-select signal inputs to DRAMPI are sampled active simultaneously. These signals become active when all of the following conditions exist at once: o M/IO#, W/R#, and D/C# outputs of the Inte1386 DX microprocessor indicate either a memory read, memory write, or code fetch.
l IDLE I DRAM READ BANK 0 NON·PIPEUNED PIPEUNED ClK ADS. DRAM REFRESH (ALWAYS BOTH BANKS) DRAM READ BANK 1 PIPELINED ~ ~JV\I\.~[v\. 'V\.~~ 'V\. 'V\.~~rv"- ~l\lVV\I\,~~ ~~I~r Y Y \J"Y ~ \J"Y Y \J" \J" \J"Y V \.FjV- Y Y Y V \J" \J"[\ 1234123 ClK2 DRAM WRITE BANK 1 PIPELINED DRAM READ BANK 1 W>L ...J1iU 1 2 3 4 I '
MEMORY INTERFACING 6.3.3.2 DRAM TIMING ANALYSIS Figure 6-7 shows the signals for bus cycles from a Inte1386 DX microprocessor to a D RAM subsystem. This figure will be used for determining the worst case logic timings for a Inte1386 DX microprocessor operating at 20 MHz. In this example, the timing for DRAM accesses are calculated for CLK2 = 40 MHz, DRAMP2 implemented using an 85C220 (12 ns) EPLD, DRAMPI implemented with a P20R8 PLD, and Refresh Address implemented with a P20RSlO PLD.
MEMORY INTERFACING WRITE CYCLE RAS V,H - - -.... I---------"'~_ _ _ _ _ _II' V,L - AD-A9 tWCR DATA 231732i6-9 Figure 6-9. Timing Waveforms (Write Cycle) 6.3.3.3 LOGIC DELAY Logic delay is the time required for an output to change with respect to an input. Devices usually have the following specifications: typical delays, maximum delays and minimum delays. For this chapter we will use worst case logic delays for the commercial operating range. 6.3.3.
MEMORY INTERFACING = 50 - 30 - 6 + 2 = 16 nanoseconds The worst case address hold time from RAS# occurs when the ROWSEL signal is at a minimum and RAS# delay is at a maximum.
MEMORY INTERFACING 6.3.3.5 DATA BUS TIMINGS The next timings to consider are the data path delays. These calculations include data buffers.
MEMORY INTERFACING T DS : Write data setup to CAS# = (2 x CLK2 period) - Inte1386 DX microprocessor Write Data Valid Delay (T12) Xcvr Prop Max + PLD RegOut Min (CAS#) + (2 x Or-gate Prop Min) = 50 - 38 - 7 + 1.5 + 6 = 12.5 nanoseconds T DH : Data hold time from CAS# active = (3 x CLK2 period) - PLD RegOut Max (CAS#) - (2 x Or-gate Prop Max) + (PLD RegOut Min (ALE) + OR-gate Prop Min) + Xcvr Disable Min = 75 - 6 - 12 + (1.5 +3) + 2 = 63.5 nanoseconds 6.3.3.
MEMORY INTERFACING WRITE BANK 1 READ BANK 0 T2 P ClK2 ClK DEN# DT/R# DATA BUS (PROCESSOR SIDE) _._D_A_TA_B_U_FF_ER_D-tR~IVI_NG___::i 80386 DRIVING CAS# DATA BUS (DRAM SIDE) -----f----.JI 231732i6-10 Figure 6-10. Avoiding Data Bus Contention The DRAMs must be able to turn off the output drivers following a read cycle in 39.5 nanoseconds to avoid the bus contention with the data being, written on the next cycle.
MEMORY INTERFACING current bus cycle can no longer be assumed valid. The 3-clock DRAM controller does not assert NA# in the first T2 but in the second T2 making it a T2p. NA# is asserted at the beginning of phase one. TNA setup = (1 x CLK2 period) - PLD RegOut Max (CAS#) = 25 - 6 = 19 nanoseconds The Intel386 DX microprocessor requires NA# setup time (T15) to be 9 ns. NA# remains asserted till READY # is returned to the Inte1386 DX microprocessor and the cycle ends.
MEMORY INTERFACING For example consider the minimum RAS# pulse width specification. Instead of: T RAS = (6 x CLK2) - PLD RegOut Max (RAS# active) + PLD RegOut Min (RAS# inactive) It would be more realistic to consider T RAS = (6 x CLK2) - PLD RegOut Skew (RAS# active-inactive) Where the skew depends on: The capacitance - The opposite going signal edges The skew would even be less for the same signal between two positive or two negative edges.
MEMORY INTERFACING • The choice of chip-select logic in the design is arbitrary. Other DRAM memorymapping schemes can be implemented by modifying the address decoding to the DRAM State PLD chip-selects. .• It is possible to deassert RAS# before the end of the cycle to improve the RAS# precharge time .
MEMORY INTERFACiNG may reduce overall system performance less than adding a wait state. Reducing the clock frequency affects the time for both external bus activity and. internal computations. The relationship between clock frequency and system performance is approximately linear. Table 4-2 gives relative performance versus wait states and operating frequency. 6.3.5 Refresh Cycles All DRAMs require periodic refreshing of their data.
MEMORY INTERFACING controller responds within 1-5 CLKs of the refresh request. The maximum latency (the difference between the longest and shortest responses) for the design is therefore 5 CLKs. This time is spread out among all 256 accesses, so 5/256 is subtracted in the above equations to account for the latency period. The counter immediately resets itself after it reaches the maximum count, regardless of this latency period.
MEMORY INTERFACING (FROM 82380) TOUTI/REF# ----t"" V" ) 1--___ HLOA Piji.----....;..--L-~ (FROM i386'" OX CPU) RFRQ .(TO ORAMP1 PLD) 231732i6-12 Figure 6-12. Refresh Request Generation In addition, the DRAMP2 PLD must be modified so that the Ready (RDY) signal is generated on refresh accesses. Finally, the OE# input of the address multiplexer should be tied low so that it never enters the high impedance state, and the row address should include the least significant address bits (AlO:3).
Cache Subsystems 7
CHAPTER 7 CACHE SUBSYSTEMS Operating at 33 MHz, the Inte1386 DX microprocessor can perform a complete bus cycle in only 60 nanoseconds, for a maximum bandwidth of 66 megabytes per second. To sustain this maximum speed, the Intel386 DX microprocessor must be matched with a high-performance memory system. The system must be fast enough to complete bus cycles with no wait states and large enough to allow the Intel386 DX microprocessor to execute large application programs.
CACHE SUBSYSTEMS 7.1 INTRODUCTION TO CACHES In a cache memory system, all the data is stored in main memory and some data is duplicated in the cache. When the processor accesses memory, it checks the cache first. If the desired data is in the cache, the processor can access it quickly, because the cache is a fast memory. If the data is not in the cache, it must be fetched from the main memory.
CACHE SUBSYSTEMS block. When a needed word is not in the cache, the cache controller moves not only the needed word from the main memory into the cache, but also the entire block that contains the needed word. A block fetch can retrieve the data located before the requested byte (look-behind), after the requested byte (look-ahead), or both. Generally, blocks are aligned (2-byte blocks on word boundaries, 4-word blocks on doubleword boundaries).
CACHE SUBSYSTEMS 31 I 24 23 I +- 2 1 I 32-BIT CACHE/DRAM PROCESSOR SELECT ADDRESS _ _ TAG 0 BYTE ENABLE 1 _ 1 6 MEGABYTE DRAM ~ 24 BITS_I DATA TAG ~ 22 BITS DATA ~ 4 BYTES FFFFFC 24682468 000000 12345678 FFFFF4 33333333 16339C 87654321 FFFFF8 11223344 - - 24682468 FFFFF8 33333333 FFFFF4 1633AO 87654321 16339C 163398 OOOOOC 000008 .... L..._ _ _'" 2816 BIT SRAM FFFFFC 11223344 4096 BIT SRAM 000004 12345678 000000 1-32BITS-t 16 MEGABYTE DRAM 231732i7-2 Figure 7-2.
CACHE SUBSYSTEMS Each direct mapped Cilche address has two parts. The first part, called the cache index field, contains enough bits to specify a block location within the cache. The second part, called the tag field, contains enough bits to distinguish a block from other blocks that .may be stored at a particular cache location. For example, consider a 64-kilobyte direcf mapped cache that contains 16K 32-bit locations and caches 16 megabytes of main memory.
CACHE SUBSYSTEMS In a system such as shown in Figure 7-3, a request for the byte of data at the address 12FFE8H in the main memory is handled as follows: 1. The cache controller determines the cache location from the 14 most significant bits of the index field (FFE8H). 2. The controller compares the tag field (12H) with the tag stored at location FFE8H in the cache. 3. If the tag matches, the processor reads the least significant byte from the data in the cache. 4.
CACHE SUBSYSTEMS 32·BIT PROCESSOR ADDRESS INDEX I+- 2 x 32K SRAM = 15 BITS--j 1+--16 MEGABYTE DRAM = 24 BITS----.j O TAG DATA INDEX TAG DATA FF 24662466 7FFC 7FF8 001 1FF 12345678 11223344 001 77777777 ~9BITS~ 1+32 BITS--j 0010 OOOC 0008 0004 0000 INDEX 7FFC 7FFB 0010 OOOC OOOS 0004 0000 ~ P.
CACHE SUBSYSTEMS The controller must also decide which block of the cache to overwrite when a block fetch is executed. There are several locations, rather than just one, in which the data from the main memory could be written. Three common approaches for choosing the block to overwrite are as follows: • Overwriting the least recently accessed block. This approach requires the controller to maintain least-recently used (LRU) bits that indicate the block to overwrite.
CACHE SUBSYSTEMS 1. PROCESSOR READ DATA; DATA NOT FOUND IN CACHE. DATA IS COPIED INTO CACHE FROM MEMORY. o-u ;3B6 OX CPU 2. PROCESSOR WRITES A NEW VALUE FOR THE DATA JUST READ. 3. LATER, ANOTHER READ CAUSES NEW DATA TO BE OVERWRITTEN. NEW DATA IS LOST. 4. PROCESSOR READS THE SAME LOCATION AS IN STEP 1. STALE DATA IS COPIED INTO CACHE. PROCESSOR GETS WRONG DATA. 231732;7·5 Figure 7-5. Stale Data Problem 7.3.
CACHE SUBSYSTEMS • In a power failure, the data in the cache is lost, so there is no way to tell which locations of the main memory contain stale data. Therefore, the main memory as well as the cache must be considered volatile and provisions must be made to save the data in the cache in the case ofa power failure. 7.3.4 Cache Coherency Write-through and write-back eliminate stale data in the main memory caused by cache write operations.
CACHE SUBSYSTEMS cache or by copying all cache writes both to the main memory and to all other caches that share the same memory (a technique known as broadcasting). Hardware transparent systems are illustrated in Figure 7-7. • Non-cacheable memory - Cache coherency is maintained by designating shared memory as non-cacheable. In such a system, all accesses to shared memory are cache misses, because the shared memory is never copied into the cache.
CACHE SUBSYSTEMS OTHER BUS MASTER _________ } NON·CACHEABLE MEMORY } CACHEABLE 1386" OX CPU CACHE ~ 231732i7·8 Figure 7-8. Non-Cacheable Memory task, and is measured in effective wait-states. Hit rate is but one of many factors which affect performance. Write policy, update policy, and coherency methods are performance factors as well. Hit rate data for various cache organizations is shown in Table 7-1.
CACHE SUBSYSTEMS 7.5 CACHE AND DMA Cache coherency is an issue one must consider when placing a DMA controller in an Intel386 DX microprocessor system. Because the DMA controller has access to main memory, it can potentially introduce stale data. As was mentioned before, stale data can be avoided in the following ways: o Implementing bus watching (snooping).
CACHE SUBSYSTEMS The main memory is updated using buffered write-through. Implementing buffered write-through is slightly more complicated than unbuffered write-through, but it has the advantage that the processor can continue to run while the DRAM write is taking place. In contrast, write-back is significantly more complicated, but may be beneficial if main memory traffic must be kept to a minimum (as in multiprocessor systems, for example).
CACHE SUBSYSTEMS 31 32·BIT PROCESSOR ADDRESS INDEX SELECT !-64K CACHE=16 BITS-! I-:z GIGABYTE DRAM = 31 BYTES~ INDEX TAG DATA FFFC FFF8 01 FF 12345678 11223344 00 01 00 87654321 11235813 13579246 I_15 BYTES-I j+32BITS+j 0008 0004 0000 (14 BITS) INDEX 11223344 FFFC FFF8 0010 OOOC OOOS 0004 0000 ~ TAG l~~ --- 0010 OOOC DATA -~ ~ '--+ 64KSRAM CACHE 12345678 11235813 FFFC FFF8 0010 OOOC 0.
CACHE SUBSYSTEMS The 82385 resides on the Inte1386 DX microprocessor local bus and interfaces directly to the Intel386 DX microprocessor. It presents a 'functional Inte1386 DX microprocessor bus (called the 82385 local bus) for the system interface. This dual bus structure and the 82385's ability to "snoop" the system interface allows the Inte1386 DX microprocessor to run locally out of the cache while another bus master has control of the 82385 local bus. 7.7.
CACHE SUBSYSTEMS ......---..........--.~ 1 i3B6'" ox CPU LOCAL BUS ~ 82385 LOCAL BUS ~ SYSTEM BUS 231732i7-11 Figure 7-11. Intel386™ OX Microprocessor/82385 System Bus Structure bus. The 82385 local bus is not simply a buffered version of the Intel386 DX microprocessor local bus, but rather is distinct from and able to operate in parallel with the Intel386 DX microprocessor local bus. The 82385 directly interfaces to the Intel386 DX microprocessor on the Intel386 DX microprocessor local bus. 7.
., .- or _. .1312 82385 CALEN TO CACHE 4 2 I CLCK2 RESET CT/R# 2 ADS# AOS# COEA#. COEB# . NA# NA# CWEAII. CWEB# LOCK# 3 -----t - REAOYl# REAOYO# WBS BROYEN# FLUSH BREAOY# MISS# BACP BEO#- BE3# A2-A31 REAOY# n ~ :::J: m - BAOEII BNA# LOSTB- BBEOH - BBE3# 00-031 I BLOCK# BAOS# CPU M/IO#. O/C#. W/R# 30 32 BHLOA 1386'· DX LOCK# 4 A2-A31 BHOLO en c OJ OTHER ~m 16 DXCPU .B READY OOE# BTlR# s: en ~ S~B+ CAB A ..
CACHE SUBSYSTEMS 7.7.2.2 Intel387 OX MATH COPROCESSOR INTERFACE Coprocessor cycles are indicated when the Intel386 DX microprocessor generates I/O cycles to addresses 800000F8H and 800000FCH. The 82385 monitors the Intel386 DX microprocessor M/IO# and A31 signals to determine when the coprocessor is being accessed. When a coprocessor access is encountered by the 82385, the cycle is effectively ignored (the 82385 remains idle) during the cycle.
CACHE SUBSYSTEMS 7.7.3 82385 Cache Organiza~ion The cache directory and management logic are integrated into the 82385. The cache data memory consists of external SRAMs which are used to store the actual code and data. The 82385 supplies all of the necessary control signals to access the cache data memory. Via a configuration input, the 82385 can be designed as either a direct mapped cache or a two-way set associative cache. 7.7.3.
CACHE SUBSYSTEMS 8Kx8 8Kx8 8Kx8
CACHE SUBSYSTEMS . 4Kx4 2x373 ADDRESS ;-- _0 ~t WEN - - -" DATA CSO#CS3# I-- ~2JA13 OED E CACHE SRAM BANK A (4Kx4) 01 I A 0 ~ " 4x245 A I B " DO~D31 'I OED DIR ;! «c 74A~~ -,-- 4 -
CACHE SUBSYSTEMS • Address Access Time (Without Buffers) The smaller of: 4xCLK2 - 386 Min Data - 385 Max CALEN - 74AS373 C-to-Q Period Setup (t21) Delay (t21b) Max Delay 4xCLK2 - 386 Min Data - 385 Max Addr - 74AS373 D-to-Q Period Setup (t21) Valid Delay (t6) Max Delay • Chip Select Access Time (With Buffers) 4xCLK2 - 386 Min Data - 385 Max CS(O-3)#- 74AS245 A-to-B Period Setup (t21) Delay (t23) Max Delay • Chip Select Access Time (Without Buffers) 4xCLK2 - 386 Min Data - 385 Max CS(O-3)# Setup (t21) Delay
CACHE SUBS,YSTEMS • Data Hold Time (Without Buffers) The smaller of: 1xCLK2 + 386 Min Data - 385 CWE# Max Period Hold (t22) Delay (t22a) 1xCLK2 Period + 386 Min Data - 385 CWE# Max Valid (t12) Delay (t22a) 7.7.4 System Interface The 82385 presents the 82385 local bus for the system interface. Since the 82385 local bus is functionally equivalent to the Intel386 DX microprocessor local bus, the' system interface is virtually identical. There are some timing differences that need to be understood.
CACHE SUBSYSTEMS of the state of A20, the memory subsystem will always see it inactive. In Protected Mode, the true state of A20 is forwarded to the system. Beginning with the 82385 (B) step, 6 ns of time will be available from the Intel386 DX microprocessor A20 valid specification to the 82385 A20 setup specification. This allows a logic gate (such as a 74AS08) to reside between the Intel386 DX microprocessor and the 82385 for the A20 line.
I/O Interfacing 8
CHAPTERS I/O INTERFACING The Intel386 DX microprocessor supports 8-bit, 16-bit, and 32-bit I/O devices that can be mapped into either the 64-kilobyte I/O address space or the 4-gigabyte physical memory address space. This chapter presents the issues to consider when designing an interface to an I/O device. Mapping as well as timing considerations are described. Several examples illustrate the design concepts. . 8.
I/O INTERFACING 8.2.1 Address Decoding Address decoding to generate chip selects must be performed whether I/O devices are I/O-mapped or memory-mapped. The decoding technique should be simple to minimize the amount of decoding logic. One possible technique for decoding memory-mapped I/O addresses is to map the entire I/O space of the Inte1386 DX microprocessor into a 64-kilobyte region of the memory space.
I/O INTERFACING OE# a·BIT 1/0 DEVICE OE# BE3# BE2# DECODE t - - _.... BE1# BEO# 231732i8·1 Figure 8-1. 32-Bit to 8-Bit Bus Conversion Another technique for interfacing with 8-bit peripherals is shown in Figure 8-1. The 32-bit data bus is multiplexed onto an 8-bit bus to accommodate byte-oriented DMA or block transfers to memory-mapped 8-bit I/O devices.
I/O INTERFACING 8.2.3 16-Bit I/O To avoid extra bus cycles and to simplify device selection, 16-bit I/O devices should be assigned to even addresses. If I/O addresses are located on adjacent word bciundaries, address decoding must generate the Bus Size 16 (BS16#) signal so that the Intel386 DX microprocessor performs a 16-bit bus cycle. If the addresses are located on every other word boundary (every doubleword address), BS16# is not needed. 8.2.
I/O INTERFACING ADDRESS LINE . =[]s iORC iiD iOWC WR . 110 DEVICE (AlONE CHIP SELECT CS CS 110 DEVICE iiD --C WIi A15 CS A14 cs iiD 1/0 DEVICE WR (B) MULTIPLE CHIP SELECTS 231732iB-2 Figure 8-2. Linear Chip Selects The bus interface control logic presented here is identical to the one used in the basic memory interface described in Chapter 6. In most systems, the same control logic, address latches, and data buffers can be used to access both memory and I/O devices.
I/O INTERFACING I I WAIT-BTATE GENERATOR ~ BUS CONTROL LOGIC t-I- rV READY. ADDRESS DECODER ,..-l\ -" ~ -,I - ADDRESS I- DATA ... -". . :..... J.. i3B6'· OX CPU A #1 ADDRESS LATCH .~ r BUS STATUS 110 DEVICE DATA TRANSCEIVER ~ V" .... ~ 110 DEVICE 112 . 231732i8-3 Figure 8·3. Basic I/O Interface Block Diagram chip-select signal becomes valid as early as possible but must be latched along with the address.
l 85C220 INT CLOCK. RESET GENERATOR RESET CLK CLK2 I J. T RESET ClK2 A05# INTR #. CS# U - f-- - IOPLD1 CLK2 CLK 10RDY NA TRIOEN =:J - IOPLD2 - ADS WTeNT1 READY WTCNT2 MilO W/R# WIR INTA INTA D/C D/C EPRD EPRDY A31 IOWA IOWR PIRECYC TIMEDLY lORD lORD BUSCYC ,...--- .READY# - RECV BUSCVC - Pf1RDY READY ALEJO RECV - i386'~ 7a A3 CS3WS CSSWS - .:::::: ::> o
"m_l® 111'tJI I/O INTERFACING A bus interface must include enough transceivers to accommodate the device with the most inputs and outputs on the data bus. If the widest device has 16 data bits and if the I/O addresses are located so that all devices are connected only to the lower half of the data bus, only two 8-bit transceivers are needed. The 74x245 transceiver is controlled through two input signals: • Data Transmit/Receive (DT/R #) - When high, this input enables the transceiver for a write cycle.
I/O INTERFACING If several I/O devices reside on the local bus, TIMEDLY # logic can be simplified by combining into a single input the chip selects for devices that require the same number of wait states. Adding wait states to some devices to make the wait-state requirements of several devices the same does not significantly impact performance. If the response of the device is already slow (four wait states, for example), the additional wait state amounts to a relatively small delay.
l PERIPHERA~ PERIPHERAL I--- RECOVERY - _RECOVERY IDLE PERIPHERAL READ -PERIPHERAl...j FLOAT NON· PIPE LINED I ADSit ADDR I I I ClK ~ PE~r~':~Al-l PER~~~~I~'E~EAD PERIPHERAL WRITE PIPELINED I I V U U ifVV U V V~ V~ J'VV ~ U U V V li"J' J V ~ J V-V J' J l1' \.l. ~ I\.L I,1l \.l. VI\l...LJ I-- rJJlJ.. JJJ.. (V' (Y' Ill,}, L\X, lXX, .
I/O INTERFACING tRR: Read (IORD#) pulse width, TWW: Write (IOWR#) Pulse Width (10 x CLK2) (10 x 25) = 248 nanoseconds tRA: - PLD RegOut Skew -2 Address hold after Read (IORD# rise) (2 x CLK2) + Latch Enable Min (2 x 25) + 5 - PLD RegOut Max - 6 + PLD RegOut Min +2 = 53 nanoseconds tAD: Data delay from Address (12 x CLK2) - xcvr.
I/O INTERFACING In Intel386 DX microprocessor systems, the instructions that provide recovery time are executed more quickly than in earlier systems. For software compatibility with earlier microprocessor generations, hardware must guarantee the recovery time. However, the circuitry to delay bus commands selectively for the specific instance of back-to-back accesses to a particular device is typically more complex than the frequency of such accesses justifies.
I/O INTERFACING 8274 FROM DATA TRANSCEIVER D7-DO FROM ADDRESS (A3 LATCH A2 DB7-DBO Al AO MODEM INTERFACE FROM ADDRESS DECODER SERIO# CS# FROM BUS (RDN CONTROLLER WRN WRH RDN 231732i8-6 Figure 8-6. 8274 Interface 8.5.2 82380 Programmable Interrupt Controller The 82380 Programmable Interrupt Controller (PIC) can be used in interrupt-driven microcomputer systems. It has 15 external and 5 internal interrupt requests.
I/O INTERFACING For a cascaded interrupt request, the 82380 PIC will output an 8-bit cascade address on the data bus during the first interrupt acknowledge cycle. A simple circuit can latch the 8-bit address and encode it to drive the CAS signals (CAS2#-CASO#) of the slave controllers. During the second interrupt acknowledge cycle, the 82380 will not drive the data bus; instead, the selected slave controller will put the interrupt vector on the data bus for the Intel386 DX microprocessor.
I/O INTERFACING data transceiver. The A2 bit, connected to the 8259A AO input, is used by the Intel386 DX microprocessor to distinguish between the two interrupt acknowledge cycles; 8259A register addresses must therefore be located at two consecutive doubleword boundaries. When an interrupt occurs, the 8259A activates its Interrupt (INT) output, which is connected to the Interrupt Request (INTR) input of the Intel386 DX microprocessor.
I/O INTERFACING interrupt request inputs to a slave controller active. The slave controller sends an interrupt request to the master controller, and the master controller interrupts the Intel386 DX microprocessor. The slave controller then returns a service-routine vector to the Intel386 DX microprocessor. The service routine must include commands to poll the third level of interrupt controllers to determine the source of the interrupt request.
I/O INTERFACING ... ) BYTE ENABLES II ". ADDRESS LATCH 1386'· DX CPU ... Ao/A1 LOGIC .... LATCHED ADDRESS '" 1386 DX CPU ADDRESS ~ ". '" ADDRESS DECODER .A 1386 DX CPU DATA ~ 'f .... 80386 STATUS ". .... DATA TRANSCEIVER , WAIT-5TATE GENERATOR J DATA 'f '" 50#/51# LOGIC ... .A ". TO 80286 COMPATIBLE PERIPHERALS r~ ...... ~ 82288 BUS CONTROLLER .. 82289 BUS ARBITER .. 231732i8-8 Figure 8-8~ 80286-Compatible Interface.
I/O INTERFACING Table 8-2.
I/O INTERFACING BEDI l l L l l BE21 H H x Ii l x If l l l '~. l H BE3I x x Ii x l l H BEDI BEll [)o---{>o21Al --- l BEll K-map for A 1 signal BEDI l l H x l l l l .x: H l BE21 H BE31 l H :x l H x x l x l l l BEll BE31 HE [~ ----..- l H BEll K-map for l6-bit BHE# signal BEDI l l BE21 H H l x l x l .H l l H l X' H x x H .x l H l H BE31 l l BEll K-map for lS-bit BlE # signal 231732i8-9 Figure 8-9.
I/O INTERFACING MIlO. - .....+-HI-.:I~.... so. DIC. --t-;~=r-\---+---.J (THESE OUTPUTS SHOULD BE lATCHED BY ClK) WIR. Sl. CHIP SELECT FOR B0286 COMPATIBLES ------4~ __, WS1 ----------~r_~ WS2 -----------..,'-~ 231732i8-10 Figure 8-10. SO#/S1# Generator Logic AD50. r1> J Q WS1 W51 K -...... I T050151 GENERATOR 85C220 , ClK WS2 1 )-- 82288 ALE ClK. ~ READY# - TO i386'· OX CPU PClK CHIP SELECT FOR 80286 COMPATIBLES 231732i8-11 Figure 8-11. Wait-State Generator Logic 8.6.
I/O INTERFACING 82289 SO# Sl# M/IO# READY# MBEN LOCK# r--- SO# LLOCK# Sl# CBRO# MIIO# BUSY# READY# BPRO# r-- SYSB BREQ# I-- LOCK# AEN# I--- I-80286 COMPATIBLE BUS I- BPRN# 82288 '--- SOH MRDC# -.........- -I---'"' Sl# MWDC# ~r-~r-- MIIO# 10RC# READY# 10WC# r+-- INTA# I-~ CENL MB 1 ~ ALE TO ADDRESS LATCH CMDLY l DT/R# TO DATA TRANSCEIVER DEN TO DATA TRANSCEIVER AEN# 231732i8-12 ,Figure 8-12. 82288 and 82289 Connections 8.6.
I/O INTERFACING FROM OTHER PERIPHERALS CLOCK GENERATOR Vee 10K!) RESET CLK2 RESET CLK2 ADS# I 82380 ADS~ CLK2 CPURST RESET READY# OPTIONAL WAITSTATE LOGIC I i386'"DX CPU READYO# READY# HOLD HOLD HLDA HLDA INT INT D/C# D/C# W/R# W/R# M/IO# M/IO# -.A- BEO-3#, A2-A31 K Do-D31 K ~ ~ t.. I I I l UU TO BUS· CONTROLLER ) BE0-3#, A2-A31 ) 00-D31 :. r TO BUS BUFFERS NOTE: INTERFACE WITHOUT CACHE 231732i8-13 Figure 8·13. Intel386™ OX Microprocessor/82380 Interface LAN.
I/O INTERFACING ,..--- - - - - - -- - - -----, I I I I I I I I I CHANNEL HOST CPU ATIENTION INTERRUPT 82586 LAN COPROCESSOR SERIAL INTERFACE 82501 ETHERNET SERIAL INTERFACE TRANSCEIVER CABLE IEEE 802.3 COMPATIBLE WORKSTATION 82C502 ETHERNET TRANSCEIVER CHIP L ______ - - - - - - - - - - - IEEE 802.3/ETHERNET LINK 231732i8-14 Figure 8-14.
I/O INTERFACING 82586 and the Intel386 DX microprocessor. In general, higher performance interfaces (requiring less servicing time from the Intel386 DX microprocessor) are more expensive. Four types of interfaces are described in this section: • Dedicated CPU • Decoupled dual-port memory • Coupled dual-port memory • Shared bus 8.6.6.1 DEDICATED CPU Dedicating a CPU to control the 82586 results in a high-performance, high-cost interface.
I/O INTERFACING Only the dual-ported SRAM is shared; the 82586 cannot access the Intel386 DX miCroprocessor core memory. The Inte1386 DX microprocessor and 82586 operate in parallel except when both require access to the SRAM. In this instance, one processor must wait while the other completes its access. At all other times, the two devices are decoupled.
I/O INTERFACING 231732i8-17 Figure 8-17. Shared Bus Interface The shared bus interface is probably the simplest and least expensive interface. However, the performance of the Inte1386 DX microprocessor may drop tremendously because the Intel386 DX microprocessor must wait for the 82586 to complete its bus operation before it can access the bus. This wait can be several hundred eLK cycles.
MULTIBUSland Intel386 ox Microprocessor 9
CHAPTER 9 MULTI BUS I AND Intel386 DX MICROPROCESSOR Previous chapters have presented single-bus systems in which a single Tnte1386 DX microprocessor connects to memory, I/O, and coprocessors. This chapter introduces the system bus, which connects several single-bus systems to create a powerful multiprocessing system. Two examples of multiprocessing system buses are the Intel MULTIBUS I, discussed in this chapter, and the Intel MULTIBUS II, discussed in Chapter 10.
MULTIBUS I AND Intel386 DX MICROPROCESSOR One method of constructing an interface between the Intel386 DX microprocessor and the MULTIBUS I is to generate all MULTIBUS I signals using only TTL and PLD devices. A simpler method is to use the 80286-compatible interface described in Chapter 8. The latter option is described in the MULTIBUS I interface example in this chapter. 9.
l . BYTE ENABLES AOIA1 LOGIC hi ADDRESS LATCH @) .... MULTIBUS ADDRESS V 35: c: !:j m c: en i386 DX CPU m A ~ ... 80386STATUS co ,)I 1386 DX CPU DATA ... ,.. SO#/S1# LOGIC DATA TRANSCEIVER l> ~ MULTIBUS DATA> z c a CD !- ~. MULTIBUS I Q) Cu , ~ ~ 82288 35: BUS CONTROLLER (; ::D o "'C ::D WAIT-STATE GENERATOR J o o ~ L--.- m 82289 BUS ARBITER en en o ::D . 231732i9-1 Figure 9-1.
MULTIBUS I AND Intel386 DX MICROPROCESSOR Inverting address latches convert the Inte1386 DX microprocessor address outputs to the active-low MULTIBUS I address bits. MULTIBUS I address bits are numbered in hexadecimal so that A23-AO on the Intel386 DX microprocessor bus become ADR17#-ADRO# on the MULTI BUS I (as shown in Figure 9-4). The BHE# signal is latched to provide the MULTIBUS I BHEN# signal.
MULTIBUS I AND Intel386 DX MICROPROCESSOR 9.2.2 Address Decoder A MULTIBUS I system typically has both shared and local memory. I/O devices can also be located either on MULTIBUS lora local bus. Therefore, the address space of the Inte1386 DX microprocessor must be allocated between MULTIBUS I and the local bus, and address decoding logic must be used to select one bus or the other.
MULTIBUS I AND Intel386 OX MICROPROCESSOR XACK# --y-- (BUS CONTROllER) ENOCYC2 r-- 82289AEN# MUlTlBUS ADSO# ] r- ~ J Q ARDY K > J Q WS1 WS1 K WS2 J"">--= 82288 ALE ...... .... ClK# I TOSO/S1 GENERATOR 85C220 ClK READY# I-- TO i386'· OX CPU PClK MOEN 231732i9-3 Figure 9-3. Wait-State Generator Logic For MULTIBUS I accesses, the wait-state generator is started by the ALE# signal from the 82288. When XACK# goes active, it is synchronized to CLK.
MULTIBUS I AND Intel386 DX MICROPROCESSOR 9.2.4 Bus Controller and Bus Arbiter Connections for the 82288 and 82289 are shown in Figure 9-4. The 82288 can operate in either local-bus mode or MULTIBUS I mode; a pullup resistor on the 82288 MB input activates the MULTIBUS I mode. Both the 82288 and the 82289 are selected by the MBEN output of the address decoder PLD. The AEN# signal from the 82289 enables the 82288 outputs. Timing diagrams for MULTIBUS I read and write cycles are shown in Figures 9-5 and 9-6.
' Ts ClK2 ClK D/C,W/~ MilO -hhlJ-UL-lLS) Tc Tc ULfUlJ L.fUl.JU1Sl.JLI1J ~ -~ -- ex ) / So-51 (PlD) t::J I s:: c ~ m \ ctJ) \ " '" r"\ »z rY MRDC o ::::J CD / c;.; CXI CO 00 @ ~ ~ ~f-- CSYNC WS2 l 0) CPURD - MBADDR, BHE ~ s:: o MBAlE ::tI X - , o C') r-"," DATA o "U ::tI '--of m tJ) tJ) XACK o V- READY I\. ENDCYC2 231732i9-5 Figure 9-5.
I ClK2 jI I D/C, WIll, M/iO 1I WSl I WS2 ! Tc ~~~ ~ ~~ 7 / I I / (3 Tcs MINIMUM) ~ .. ,,- iO-si (PLD) MWfC ~ MBDEN ! ; I I I MBAlE I I I I I MB AQ!!!!, BHE ; I i I I ~ I ( READY I I ENDCYCZ I I I I I iiACR - s:c: ~ iii c: (J) I I » z I c I I \ I I .. ~ --..; 1-\ i I I DATA / \.
MULTIBUS I AND Intel386 DX MICROPROCESSOR 9.3 TIMING ANALYSIS OF MULTIBUS I INTERFACE The timing specifications for the MULTIBUS I are explained in the MULTIBUS® I Specification, Order Number 9800683. Table 9-1 lists the MULTIBUS I parameters that relate to the Inte1386 DX microprocessor system. These calculations are based on the assumption that 74ALS580 latches and 74F544 transceivers are used for the MULTIBUS I address and data interface.
MULTIBUS I AND Intel386 DX MICROPROCESSOR Each processing subsystem contains its own 82289 Bus Arbiter. The Bus Arbiter directs , its processor onto the bus and allows higher and lower priority bus masters to access the bus. Once the bus arbiter gains control of MULTIBUS I, the Inte1386 DX microprocessor can access system resources. The bus arbiter handles bus contention in a manner that is transparent to the Intel386 DX microprocessor.
MULTIBUS I AND Intel386 OX MICROPROCESSOR SERIAL PRIORITY RESOLVING TECHNIQUE 1 74146 4 PRIORITY ENCODER 74136 3T06 ; DECODER 4 PARALLEL PRIORITY RESOLVING TECHNIQUE 231732i9-7 Figure 9-7. Bus Priority Resolution In addition, the bus arbiter can switch between modes 2 and 3, based on the type of bus cycle. Figure 9-8 shows the strapping configurations required to implement each of these four techniques.
MULTIBUS I AND Intel386 DX MICROPROCESSOR 82289 82289 RESET RESET ALWA'fS/ClIQ[CK ":' MODE 2 MODE 1 82289 82289 RESET RESET RESET RESET 'Q MODE 3 ~ D PARALLEL I/D OR ADDRESSABLE LATCH MULTIBUS . BCLK ENABLE . * WHEN LOW, 82289 IN WHEN HIGH, 82289 IN MODE 3; MODE 2 231732i9-8 Figure 9-8. Operating Mode Configurations subsystems waiting to use MULTIBUS I.
MULTIBUS I AND Intel386 DX MICROPROCESSOR 9.4.3 MULTIBUS I Locked Cycles Locked bus cycles for the local bus are described in Chapter 3. In locked bus cycles, the Intel386 OX microprocessor asserts the LOCK# signal to prevent another bus master from intervening between two bus cycles. In the same manner, an Intel386 OX microprocessor processing subsystem can assert the LLOCK# output of its bus arbiter to prevent other subsystems from gaining control of MULTIBUS 1.
MULTIBUS I AND Intel386 DX MICROPROCESSOR • Some slave interrupt controllers reside on local buses, and other slave interrupt controllers reside on MULTIBUS I. In this case, the appropriate bus for the interruptacknowledge cycle depends on the cascade address generated by the master interrupt controller. In the first two configurations, no decoding is needed because all interrupt acknowledge cycles are directed to one bus.
MULTIBUS I AND Intel386 OX MICROPROCESSOR r--;8259A 0, MASTER~~~~I-~_ _""'~~ J, 1.IN~TA~":CA~Sj2111--'4A2_ iT i: _ OF 74530 t-----t»-+-J"¢l~~~ ~... CASVALlD(l) (74500 74AlS580 -L__r:::::::::::~sre L-1___~Aa~IA9~Al~0L-_~~ '~-.--~---~ ~ VMt Of" ,/ (FROM SLAVE INTERRUPT CONTROLLER) A20-Ao _ _ ,...-t'-----t .-----<~I SYSB/R£SI! 1< AENr-- 82289 BUS ARBITER INTA MCE CENL .....-------bo-t>>-+-lcMOLY ...
MULTIBUS I AND Intel386 DX MICROPROCESSOR ox CPU OATABUS 13B6~ BUS CONTROL BUS CONTROL 74F373 LE ALE~ +-.......-_. )0.4............. 74ALS5BO MULTIBUS BHEN MULTIBUS ADRO OE ":'" 231732i9-10 Figure 9-10. Byte-Swapping Logic 9.5.3 Bus Timeout Function for MULTIBUS I Accesses The MULTIBUS I XACK# signal terminates ail Inte1386 DX microprocessor bus cycl'f by driving the wait-state generator logic.
MULTIBUS I AND Intel386 DX MICROPROCESSOR ., ~ .....a ALE CLK2 0 ~ ..... - a """- ~ C I- READY# a 0 Q '-- TIMEOUT# 231732i9-11 Figure 9-11. Bus-Timeout Protection Circuit 9.5.4 MULTIBUS I Power Failure Handling The MULTJBUS I interface includes a Power Fail Interrupt PFIN signal to signal an impending system power failure. Typically, PFIN# is connected to the non-maskable interrupt (NMI) request input of each Inte1386 DX microprocessor.
MULTIBUS I AND Intel386 DX MICROPROCESSOR The iLBX bus interface requires the generation of AI, AO, and BHE# from the Inte1386 DX microprocessor BE3#-BEO# outputs .. The iLBX connector contains 24 address bits (AB23-ABO) and 16 data bits (DBlS-DBO), which are taken from the buffered address lines (A23-AO), and data lines (DIS-DO) of the Inte1386 DX microprocessor local bus. BHE# is inverted and buffered to provide the Byte High Enable (BHEN) signal.
MULTIBUS I AND Intel386 DX MICROPROCESSOR 9.7 DUAL-PORT RAM WITH MULTIBUS I A dual-port RAM is a memory subsystem that can be accessed by both the Inte1386 DX microprocessor, through its local bus, and other processing subsystems, through the MULTIBUS I system bus. Dual-port RAM offers some of the advantages of both local resources and system resources. It is an effective solution when using only local memory or only system memory would decrease system cost and/or performance significantly.
MUL TIBUS II and Intel386 OX Microprocessor 10
CHAPTER 10 MULTIBUS 'II AND Intel386 OX MICROPROCESSOR Standard bus interfaces guarantee compatibility between existing and newly developed systems. This compatibility safeguards a user's hardware investment against obsolescence even in the face of rapidly advancing technology. The MULTIBUS I standard interface has proven its value in providing flexibility for the expansion of existing systems and the integration of new designs.
MULTIBUS II AND Intel386 OX MICROPROCESSOR The iPSB supports four address spaces per bus agent (a board that encompasses a functional subsystem). The conventional I/O and memory address spaces are included, plus two other address spaces that support advanced functions: . • A 255 address message space supports message passing. Typically, a microprocessor performs interprocessor communications inefficiently.
l @ ARBITRATION CYCLE :s:: c: ~ m c: CJ) = » z TRANSFER CYCLE .,.----"'\, .,.----"\, c :::J CD W co Q) ~ a Col ~ :s:: (5 :::D o "D EXCEPTION CYCLE :::D o om CJ) CJ) o :::D 231732i10-1 Figure 10-1.
MULTIBUS II AND Intel386 DX MICROPROCESSOR 10.2.1 iPSe Interface Each bus agent must provide a means of transferring data between its Intel386 DX microprocessor, its interconnect registers, and the iPSB bus. The location of bus interface logic to meet this requirement is shown in Figure 10-2. A full-featured subsystem may also include provisions for the message passing protocols used by the iPSB bus.
MULTIBUS II AND Intel386 DX MICROPROCESSOR The BAC signals can be divided into three functional groups: • iPSB interface • Local bus interface • Register interface with the Inte1386 DX microprocessor The iPSB interface signals perform mainly arbitration and system control. Five bidirectional Arbitration signals (ARBS-ARBO) are used during reset to read a cardslot ID and arbitration ID from the CSM, and during arbitration cycles to output the arbitration ID for priority resolution.
MULTIBUS II AND Intel386 OX MICROPROCESSOR The bus agent that receives a transfer cycle from the bus owner must have its BAC enabled by an active SELECT input. Errors detected by the replying agent are encoded by its MIC on the AGERR2-AGERRO inputs to its BAC so that the BAC can drive the SC7#-SC5# lines accordingly. If an error occurs, the requesting agent notifies the Intel386 DX microprocessor through the EINT signal.
MULTIBUS II AND Intel386 DX MICROPROCESSOR decoder distinguishes between local, interconnect, and iPSB accesses. PLDs control the buffering of signals between the Intel386 DX microprocessor, BAC, MIC, 8751 Microcontroller, and iPSB bus. 10.3 LOCAL BUS EXTENSION (iLBX II) The iLBX II bus extension is a high-speed execution bus designed for quick access to off-board memory.
Physical Design and Debugging 11
CHAPTER 11 PHYSICAL DESIGN AND DEBUGGING To maximize the performance of high-speed Intel386 DX processor systems, it is recommended that optimum design guidelines be followed. This chapter outlines the basic design issues, ranging from power and ground issues to achieving proper thermal environment for Intel386 DX microprocessor. 11.1 GENERAL DESIGN GUIDELINES The performance and proper. operation of any high-speed system greatly depends upon appropriate physical layout.
PHYSICAL DESIGN AND DEBUGGING The worst-case power dissipation of any VLSI device is estimated in the following manner: 1. To estimate typical power dissipation for each circuit element: P G : Typical power dissipation for internal logic gates (mW) PI/a: Typical power dissipation for I/O buffers (mW) 2. To estimate total typical power dissipation: PT = PG + PliO (mW) ... (1) where P T is the total typical power dissipation (mW) 3. To estimate the worst case power dissipation: Pd = PT X C v (mW) ..
PHYSICAL DESIGN AND DEBUGGING high-performance systems. Logic designers can use techniques designed to minimize this problem. One technique is to reduce capacitance loading on signal lines and provide optimum power and ground planes. Power and ground lines have inherent inductance and capacitance, which affect the total impedance of the entire system.
PHYSICAL DESIGN AND DEBUGGING roo®' Lo Irca zo=J~ Co 231732i11-1 Figure 11-1. Reduction in Impedance 11.3 DECOUPLING CAPACITORS The advanced, high-speed CMOS logic families available today have much faster edge rates than do the older, slower logic technologies. The switching speeds and drive capability needed to provide high performance systems are also associated with increased noise levels. Some noise levels are inconsequential because they fall within the switching times of the other devices.
PHYSICAL DESIGN AND DEBUGGING GNO 5v Ie Packages \. I I ~ 1 Oecoupling U·'~" GN0L---T-_ _+- 231732i11-2 Figure 11-2. Typical Power and Ground Trace Layout for Double-Layer Boards or other boards in a multi-board system. It is necessary to match the supply's impedance to that of the components in order to-lessen the potential for voltage drops that can be caused by Ie edge rates, ground- or signal-level shifting, or noise induced currents or voltage reflections.
PHYSICAL DESIGN AND DEBUGGING 5V Trace s x/1 IV ?I / // ?\" x/1 I I / " I I i,U GND GND /' 7'\'< I I I ?\ S r-, I I / r, =s GND GND /.-- 7'1'< / Return or . / ,GNDTrace // X I 7'1 I / I I, , GND ~ l./II 5V I I, S" GND --.A 5V 231732i11-3 Figure 11-3. Orthogonal Arrangement systems. This capacitor is typically placed at the supply's entry point to the board.
PHYSICAL DESIGN AND DEBUGGING A _ -......--.,---' 3_--+--_..... f-----ey A4 231732i11-4 Figure 11-4. Circuit without Decoupling Most popular logic families require that a capacitor of 0.01 f.LF to 0.1 f.LF (RF grade) be placed between every two to five packages, depending on the application. For high-speed CMOS logic, a good rule of thumb is to place one of these bypasses between every two to three ICs, depending on the supply voltage, the operating-speed and EMI requirements.
PHYSICAL DESIGN AND DEBUGGING [1 0 0 ;386 ,. OX CPU m 0 0 ~ 0 rt] =0.1 ~F =1.0 ~F ~ 231732;11·5 Figure 11-5. Decoupling with Surface Mount Capacitors ~o~o -D-mJ-D- -tm;386 ,. OX CPU ~ CJ~ -CJ- ~ =1.0~F o =0.1 ~F O~O~ 231732;11·6 Figure 11-6. Decoupling with Leaded Capacitors 11.4 HIGH FREQUENCY DESIGN CONSIDERATIONS The overwhelming concern in dealing with high speed technologies is the management of transmission lines.
PHYSICAL DESIGN AND DEBUGGING The following sections discuss the negative effects of a transmission line that occur when operating at higher frequencies. In higher frequency design the reflection and cross talk effects are inevitable; it is impossible to design optimum systems without accounting for these effects. Later sections include a discussion of techniques that can minimize these effects. . 11.4.
PHYSICAL DESIGN AND DEBUGGING 11.4.1.1 TRANSMISSION LINE TYPES Although many different types of transmission lines (conductors) exist, those most commonly used on the printed circuit boards are micro strip lines, strip lines, printed circuit traces, side-by-side conductors and flat conductors. 11.4.1.1.1 Micro Strip Lines The micro strip trace consists of a signal plane that is separated from a ground plane by a dielectric as shown in Figure 11-7.
PHYSICAL DESIGN AND DEBUGGING 11.4.1.1.2 Strip Lines A strip line is a strip conductor centered in a dielectric medium between two voltage planes. The characteristic impedance is given theoretically by the equation below: ZO = (601 ve; In (5.98bhr (0.8 W + t)) ohms where b = distance between the planes for controlled impedance as shown in Figure 11-8. The propagation. delay .is given by the following formula tpd = 1.017 \l'Et.ns/ft For G-I0 fiberglass epoxy boards (e r 2.27 ns/ft. = 5.
PHYSICAL DESIGN AND DEBUGGING 11.4.2 Impedance Mismatch As mentioned earlier, the impedance of a transmission line is a function of the geometry of the line, its distance from the ground plane, and the loads along the line. Any discontinuity in the impedance will cause reflections. Impedance mismatch occurs between the transmission line characteristic impedance and the input or output impedances of the devices that are connected to the line.
PHYSICAL DESIGN AND DEBUGGING B 231732i11-10 Figure 11-10. Loaded Transmission Line The magnitude of a reflection is usually represented in terms of a reflection coefficient. This is illustrated in the following equations: T =. V,lVi = Reflected voltage/Incident voltage Tsource = (Zsource - Zo)/(Zsource + Zo) Reflection voltage Vr is given by Vi' the voltage incident at the point of the reflection, and the reflection coefficient. The model transmission line can now be completed.
PHYSICAL DESIGN AND DEBUGGING This phenomenon continues infinitely, but it is negligible after 3 or 4 reflections. Hence: Each reflected waveform is treated as a separate source that is independent of the reflection coefficient at that point and the incident waveform. Thus the waveform from any point and on the transmission line and at any given time is as follows: Each reflection is added to the total voltage through the unit step function H(t).
PHYSICAL DESIGN AND DEBUGGING A B T~O Tpd 2Tpd 3Tpd 4Tpd 5Tpd rL3r s2V"" ;::. Vr5 6Tpd ... x 231732i11-11 Figure 11-11. Lattice Diagram The appropriate reflection coefficients can be calculated as follows: f source f load Va Vr1 Vr2 Vr3 Vr4 Vr5 V'6 Vr7 75)/ (30 + 75) = -0.42857 - 75)/ (100 + 75) = 0.14286 = VsX 75/(75 + 30) = 2.64286 V = 2.64286 X 0.14286 = 0.37755 V = 0.37755 X -0.42857 = -0.16181 V = -0.16181 X 0.14286 = - 0.02312 V = -0.02312 X -0.42857 = 0.00991 V = 0.00991 X 0.14286 = 0.
PHYSICAL DESIGN AND DEBUGGING A B VIB.I) VIA,I) 1= 0 ....-_ _ 2.857 V 2T... 2.845V 4Tpo l'----;:;.:.:~:.-----..-.r Tpo 3.02 V 1'-_--~~~:::.----13T. . 2.835V 1_---.::::.~~~----15TPd2.847v 2.846 V 6Tpd . . . . -_ _ 7T... 2.846 V 231732i11-12 Figure 11-12. Lattice Diagram Example Table 11-1. Voltage at End Points A and B tpd 0 1tPd 2tpd 3tpd 4tpd 5tpd 6tpd 7tpd . V(A,t) V(8,t) 2.64286 2.64286 2.85860 2.85860 2.84539 2.84539 2.84620 2.84620 0 3.02041 3.02041 2.83549 2.83549 2.84681 2.
PHYSICAL DESIGN AND DEBUGGING the transmission line from the source. The terminating' impedance combines with' the destination input circuitry to produce a load that closely matches the characteristic impedance of the line (board traces have characteristic impedances in the range of 30 ohms to 200 ohms). The calculation of characteristic impedance was already discussed. Impedance of the printed circuit board backplane connectors have the impedance in the same range as the traces (Le., 30 to 200 ohms) ..
PHYSICAL DESIGN AND DEBUGGING -t> Zo =750 A • "NV'v RL Driver B • (~ L=9'~) C {>Receiver 231732i11-13 Figure 11 -13. Series Termination One main advantage of series termination is that only logic power dissipation results so . that lower overall power is required than with other techniques. There is one penalty, however, in that the distributed loading along the transmission line cannot be used because only half of the voltage waveform is travelling down the line.
PHYSICAL DESIGN AND DEBUGGING Since the input impedance of the device is high compared to the characteristic line impedance, the resistor and the line function as a single impedance with a magnitude that is· defined by the value of the resistor. When the resistor matches the line impedance, the reflection coefficient at the load approaches zero, and no reflection will occur. One useful approach is to place the termination as close to the loading device as possible.
PHYSICAL DESIGN AND DEBUGGING Receiver Driver 231732i11-15 Figure 11·15. Thevenins Equivalent Circuit from its reduced power consumption, is its flexibility. The received signal amplitude can be adjusted to match the switching threshold of the receiver simply by changing the value of the terminating resistor. This is a very useful technique for interconnecting the logic devices with long lines. 11.4.2.1.5 A.C.
PHYSICAL DESIGN AND DEBUGGING Receiver Driver 231732i11-16 Figure 11-16. A.C. Termination 11.4.2.1.6 Active Termination These terminations consist of resistors that are connected between the inputs and outputs of buffer drivers as shown in Figure 11-17. The main advantage of this technique is that it can tolerate large impedance variations and this tolerance is valuable when tri-state drivers are connected to backplane buses.
PHYSICAL DESIGN AND DEBUGGING as other terminations. A common solution is to place active terminations at both ends of the bus. This helps to maintain the uniform drive levels along the entire length of the bus, and it reduces crosstalk and ringing. Table 11-2 shows the comparisons of different termination techniques. 11.4.2.1.
PHYSICAL DESIGN AND DEBUGGING L=g" Trace Is Microstrip 231732i11-18 Figure 11-18. Impedance Mismatch Example Since Zs = 10 ohms, the termination techniques described previously will be needed to match the difference of 45.6 ohms. One method is to use a series terminating resistor of 45.6 ohms or use A.C. termination where R=55.6 ohms and C=O.3 J.,LF. The terminated circuit of Figure 11-18 is shown in Figure 11-19. 11.4.2.
PHYSICAL DESIGN AND DEBUGGING SOURCE 231732i11-20 Figure 11-20. Daisy Chaining 11.4.2.3 gO-DEGREE ANGLES Another major cause of reflections are 90-degree angles in the signal paths, which cause an abrupt change in the signal direction. It promotes signal reflection. For highfrequency layout of designs, avoid 90-degree angles and use 45 or 120-degree angles as shown in Figure 11-21. 11.4.2.
PHYSICAL DESIGN AND DEBUGGING frequency design, including interference. In general, interference occurs when electrical activity in one conductor causes transient voltage to appear in another conductor. Two main factors increase the interference in any circuit: 1. Variation of current and voltage ,in the lines causes frequency interference. This interference increases with frequency. 2. Coupling occurs when conductors are in close proximity.
PHYSICAL DESIGN AND DEBUGGING C T Parasitic Capacitance (Parasitic Capacitance) I J C Chassis Ground 231732i11-22 Figure 11-22. Typical Layout (which reduces its effective impedance), this noise can be minimized. This technique also provides a secondary advantage in that it forms a shield which reduces the emissions of other circuit traces, particularly in multi-layer circuit boards.
PHYSICAL DESIGN AND DEBUGGING The design of effective decoupling and bypass schemes centers on maximizing the charge stored in the circuit bypass loops while minimizing the inductances in these loops. Some other precautions that can minimize the EMI are as follows: • Running a ground line in between two adjacent signal lines. The extra line should be grounded at both ends. • The address and data buses can also be separated by ground lines.
PHYSICAL DESIGN AND DEBUGGING 11.4.3.3 ELECTROSTATIC INTERFERENCE We have discussed two types of coupling, namely inductive and radiative coupling which are responsible for creating electromagnetic interference. A third, known as capacitive coupling, occurs when two equipotential parallel traces are separated by a dielectric and act as a, capacitor.
PHYSICAL DESIGN AND DEBUGGING One way to minimize this is by decreasing the lengths of the interconnections. Overall route lengths are shorter in multilayer printed-circuit boards than in double layer boards because ground and power traces are not present. In addition to adding ground planes, a routing program can help to shorten the paths. The guidelines discussed so far are prominent at higher operating frequencies.
PHYSICAL DESIGN AND DEBUGGING 74AS244 2 66.67 MHz or 50 MHz OSC 18 Y1 A1 4 6 A2 ACLK2 16 Buffer Y2 14 A3 Y3 A4 Y4 12 8 BCLK2 G 231732;11·24 Figure 11·24. Typical Intel386™ DX Microprocessor Clock Circuit Vee-O.BV CLK2 [ 2.0V O.BV 231732;11·25 Figure 11·25. CLK2 Timing Diagram The clock input requirements for Intel386 DX microprocessor systems are more stringent than those for many commonly used TTL devices. The clock timings are shown in Figure 11-25 and Table 11-3. 11.6.
PHYSICAL DESIGN AND DEBUGGING Table 11-3. Timing Specifications for CLK2 Symbol t1 t2a t2b t3a t3b t4 t5 Parameter 25 MHz i386'" OX CPU Operating Frequency Min 4 CLK2 Period CLK2 High Time 20 7 CLK2 High Time CLK2 Low Time CLK2 Low Time 4 7 CLK2 Fall Time CLK2 Rise Time Unit Max 33 MHz 1386 OX CPU Min MHz B Max 33.3 ns 15.0 62.5 ns ns ns 6.25 4.5 6.25 ns ns 4.5 7 7 ns 25 125 5 4 4 Unit Notes MHZ ns Half of CLK2 Frequency ns at 2V ns ns ns at3.7V at 2V atO.BV ns ns 3.
PHYSICAL DESIGN AND DEBUGGING Clock Source Series Termination 231732i11-27 Figure 11-27. Star Connectipn 11.7 THERMAL CHARACTERISTICS The thermal specification for the Inte1386 DX microprocessor defines the maximum case temperature. This section describes how to ensure that an Intel386 DX microprocessor system meets this specification. Thermal specifications for the Intel386 DX microprocessor are designed to guarantee a tolerable temperature at the. surface of the Inte1386 DX microprocessor chip.
PHYSICAL DESIGN AND DEBUGGING Case temperature calculations offer several advantages over ambient temperature calculations: • Case temperature is easier to measure accurately than ambient temperature because the measurement is localized to a single point (top .center of the package).
PHYSICAL DESIGN AND DEBUGGING Room in the system should be included for the following physical features to aid debugging: • Two switches: one for generating the RESET signal to the Intel386 DX microprocessor and one for tying the READY# signal high (negated).
PHYSICAL DESIGN AND DEBUGGING EPROMs, static RAMs, and peripherals all interface in much the same way. The EPROM interface is the simplest because EPROMs are read-only devices. RAM interfaces must support byte addressability during RAM write cycles. Therefore, RAM write enables for each byte of the 32-bit data bus must be controlled separately. The BS16# signal must be activated when the current bus cycle communicates over a 16-bit bus.
PHYSICAL DESIGN AND DEBUGGING Also, after reset (until the Intel386 DX microprocessor executes an intersegment JMP or CALL instruction), the physical base address of the code segment is set internally to FFFFOOOOH. Therefore, the physical address of the first code fetch after reset is always FFFFFFFOH. The simple diagnostic program must begin at this location. 11.8.4 Building and Debugging a System Incrementally When designing an Inte1386 DX microprocessor system, the designer plans the entire system.
PHYSICAL DESIGN AND DEBUGGING Mter installing the EPROMs, the READY# line should be tied high (negated) so that the Inte1386 DX microprocessor begins its first bus cycle after reset and then continues to add wait states. While the system is in this state, the circuit should be probed to verify signal states, using a voltmeter or oscilloscope probe.
PHYSICAL DESIGN AND DEBUGGING PAGE 66,132 LATCH EQU 0C8H GOOD-SIGNAL BAD-SIGNAL EQU EQU 0AAH 055H , EQUATES ;PRESUMES A HARDWARE ;LATCH IS AT I/O ADDR C8H CODE TO VERIFY ABILITY TO WRITE AND READ RAM CORRECTLY INITIAL_CODE ASSUME CS:INITIAL_CODE SEGMENT ORG 0F000H TSLLOOP: MOV MOV MOV MOV JMP BX, 0000H DS, BX rBX], 5473H rBX]+2, 2961H READ READ: CMP rBX], 5473H JNE CMP BADRAM rBX]+2, 2961H JNE BADRAM MOV OUT JMP BADRAM: ;THIS IS INTENDED TO BE LOCATED ;AT PHYSICAL ADDRESS FFFFF000H
PHYSICAL DESIGN AND DEBUGGING This program can be written in ASM86 assembly language. Because the primary purpose of this program is to exercise the system hardware quickly, the InteI386 DX microprocessor is not tested extensively, and Protected Mode is not enabled. The diagnostic software verifies the ability of the system to perform bus cycles. The .
PHYSICAL DESIGN AND DEBUGGING ·PAGE 66,132 EQUATES 00C8 00AA 0055 LATCH GOOLSIGNAL BALSIGNAL EQU EQU EQU 0C8H 0AAH 055H CODE TO VERIFY ABILITY TO WRITE AND READ RAM CORRECTLY 0000 INITIAL_CODE F000 ASSUME CS:INITIAL_CODE SEGMENT ORG 0F000H F000 F003 F005 F009 F00E BB 8E C7 C7 EB 0000 DB 07 5473 47 02 2961 01 90 TSLLOOP: MOV MOV MOV MOV JMP BX, 0000H DS, BX [BX1, 5473H [BX1+2, 2961H READ F011 F015 F017 F01C 81 75 81 75 3F 5473 0D 7F 02 2961 06 READ: CMP JNE CMP JNE [BXl, 5473H BADRAM [
Test Capabilities 12
CHAPTER 12 TEST CAPABILITIES The Inte1386 DX microprocessor contains built-in features that enhance its testability. These features are derived from signature analysis and proprietary test techniques. All the regular logic blocks of the Intel386 DX microprocessor, or about half of all its internal devices, can be tested using these built-in features. The Intel386 DX microprocessor testability features include aids for both internal and board-level testing. This chapter describes these features. 12.
TEST CAPABILITIES TOEAX 231732i12-1 Figure 12-1. Intel386™ OX Microprocessor Self-Test The self-test provides lOO-percent coverage of single-bit faults, which statistically comprise a high percentage of total faults. 12.1.2 Translation Lookaside Buffer Tests The on-chip Page Descriptor Cache of the Inte1386 DX microprocessor stores its data in the TLR (Cache operation is discussed fully in Chapter 7.) The linear-to-physical map-.
TEST CAPABILITIES retrieved from the RAM and added to the 12 bits of the Offset field of the linear address, creating a 32-bit physical address. If a miss (no match) occurs, the Intel386 DX microprocessor must bring the Page Directory and Page Table values into the TLB from memory. The Inte1386 DX microprocessor provides an interface through which to test the TLB.
TEST CAPABILITIES 12 11 31 o ' 5 4 ~------------~--~~~~~ LOOKUP/ WRITEN TAG LINEAR ADDRESS COMMAND REGISTER 12 11 31 5 4 3 2 1 0 ~I PHYSICAL ADDRESS DATA REGISTER MIT/REPLACEMENT MISS POINTER OR REPLACEMENT BIT 231732i12-2 Figure 12-2. TLB Test Registers The complement of the Dirty, User, and Writable bits are provided to force a hit or miss for TLB lookups. A lookup operation with a bit and its complement both low is forced to be a miss; if both bits are high, a hit is forced.
TEST CAPABILITIES The TLB lookup operation progresses as follows: • The linear address and tag values are written to the command register, as well as a 1 value for bit O. • New values for the hit/miss bit and replacement pointer are written to bits 4-2 in the data register. If the hit/miss bit (bit 4) is 1, bits 31-12 contain the physical address from the TLB. Otherwise, bits 31-12 are undefined.
Local Bus Control PLD Descriptions A
APPENDIX A LOCAL BUS CONTROL PLD DESCRIPTIONS The bus controller is implemented in two PLDs. One PLD (called IOPLD1) follows the Intel386 DX microprocessor status lines and initiates I/O and EPROM accesses. The second PLD (IOPLD2) contains the bus cycle tracking state machine and determines the number of wait states for I/O system accesses. EPROMs and peripherals are usually arranged with 16-bit data bus interfaces. This subsystem asserts BS16# for all accesses to the I/O and EPROMs.
LOCAL BUS CONTROL PLD DESCRIPTIONS devices requiring different numbers of wait states are in the system, the TIMEDLY# state machine must check the chip select wait state pins (CSIWS#, CS3WS#, , CS5WS#). These signals are generated from the mapping of the I/O devices. The 8259A interface has not been built or tested. PLD EQUATIONS The equations for 10PLDI, IOPLD2, and the RESET/CLOCK PLDs are shown in Figures A-I, A-2, and A-3, respectively.
LOCAL BUS CONTROL PLD DESCRIPTIONS module iopldl; flag '-r3'; flag '-ul'; title 'eprom/io controller intel corporation' "This 85C221l generates IORD#, IOWR#, [PRD#, and INTA# for "the peripheral subsystem. It decodes and responds to "the following bus cycles: i/o read, i/o write, memory "read (with A31 high), interrupt acknowledge, halt, "and shutdown. U7 device '[1l321l'; h,l,c,x = 1,1l, .C., .X.
LOCAL BUS CONTROL PLD DESCRIPTIONS "io state machine state_diagram (iord,iowr,eprd,inta,iordy,recv1; state idle: case na & !buscyc & pa31 & !wr & clk: epreadl; na & !buscyc & !pa31 & !mio & dc & wr & clk: iowritel; na & !buscyc & !pa31 & !mio & dc & !wr & elk: ioreadl; na & !buscyc & !pa31 & !mio & !dc & !wr & clk: intakl; na & !buscyc & mio & !dc & wr & clk: iowrite2; "halt endcase; state state state state epreadl: epread2: iowritel: iowrite2: state state state state state ioreadl: ioread2: intakl: int
LOCAL BUS CONTROL PLD DESCRIPTIONS [e,h,h,h,h,h,h,h,h,ll -> [h,h,h,h,h,hl; [e,h,h,h,h,h,h,h,h,ll -> [h,h,h,h,h,hl; , 'idle "idle end iopldl; eprom/io controller intel corporation Equations for Module iopldl Device U7 - Reduced Equations: !trioen := (!elk.
LOCAL BUS CONTROL PLD DESCRIPTIONS module iopld2; flag '-r3'; title 'eprom/io wait state timer and bus cycle tracking' "This P2BR6 determines the number of wait states and recovery "states for 1/0 reads, 1/0 writes, eprom reads, and Interrupt "ackn.wledge cycles. Choose the number of wall slales for each "peripheral by Ihe chip selects U8 device 'p20r8'; h,I,c,x·I,O,.C.,.X.
LOCAL BUS CONTROL PLD DESCRIPTIONS "10 cyclo Ilmor ,1.lo.dlagram [llmedly,wlcnI2,wlcnll,wlcnI0]; .1.le Id]e if «!Iord I !Iowr I !Inlo) & clk) Ihon lim03 0150 If (!eprd & clk) Ihen IIm02 o],o,lf (!recv & clk) Ihen IIme2 ol.e Idle; • Ia Ie ,10 Ie ,1.10 ,1.le ,Iole ,1010 .1.le • I. Ie I 1m 0 7 : limeS: limeS: I 1m e 4 : Ilme3: I 1m 0 2 : I I mol: IImeup: if II If If If If if if clk clk clk clk c] k c] k clk Ii 0 Ihen I hen Ihon I hen I h0n I hen I hen rd & limoS 01.
LOCAL BUS CONTROL PLD DESCRIPTIONS test-veeton ([clk2,clk,iord,lowr,eprd,inta,recvl [c,h,h,h,h,h,hl [c,h,h,h,h,h,hl [c,h,h,h,h,h,hl [c,h,h,h,h,h,hl ; ; [h I ; [h I; [h I ; [h I; " I die " I die II i dIe [hi; [hi; [hi; [hi; [hi; read read read "ia read [c,h,l,h,h,h,hl [c,h,l,h,h,h,hl [c,h,l,h,h,h,hl " " " [hi; [hi; [hi; [e,h,l,h,h,h,h] ~ [11; [c,h,h,h,h,h,11 " [hi; "Interrupt "interrupt "interrupt "Interrupt " I die [c,h,h,l,h,h,hl [c,h,h,l,h,h,hl [c,h,h,l,h,h,hl [c,h,h,l,h,h,hl [c,h,h,h,
LOCAL BUS CONTROL PLD DESCRIPTIONS eprom/io wail slale limer and bus cycle Irapking Equalions for Module iolime Device - ua Reduced Equalions: aleio :" !(!aleio , !elk , elk' !inla , elk , !iord , elk !iowr); Ilmedly :" !C!elk , I elk' , !eprd I !inla I !lord I !iowr !Iimedly , Ilmedly , & !Iimedly , !Iimedly '!Ilmedly & !Iimedly wlenlO & wlenll , !wlenlO & wlenll & , wlenlO & wlenll wlenll , wlenlO wlenll wlenlO wi e nil wlenlO wlenl2 :" !C!elk , limedly , !wlenl2 I Ilmedly , !wlenlO ,
LOCAL BUS CONTROL PLD DESCRIPTIONS module clock; flag '-r3'; flag '-ul'; title 'clock generator intel corporation' "This 85C220 divides the doulbe frequency ClK2 input "by two to generate a single frequency ClK. It also "provides synchronous reset outputs from an asynch"ronous reset input. The lowest two bits of the DRAM "refresh timer are included in this PlD. U2 device 'E0320'; h,l,c,x = 1,0, .C., .x.
"M_I® II 1'eI LOCAL BUS CONTROLPLD DESCRIPTIONS test.vector5.([clk2,refreql [ c , II [ c , II [ c , II [ c , II [ c , II [ c , II [ c , II [ c , II [ c , II [ c , II [ c , II [ c ; II [ c , II [c, I I [c, II [ c , II [c, h I [c, h I [c, h I [c, hI [c, h I [c, h I [c, h I [c, hI [c, hI [ c ,h I ..... .. .... . . .. .. . . ... . . . . . . . . .. [c, h I [c, h I [c, h I [c, h I [c, h I [ c ,h I [ c , II [ c , II [ c , II [c, I I [c, I I [ c , II end clock; . .. ... .. .. .. ..
LOCAL BUS CONTROL PLD DESCRIPTIONS clock generator Intel corporation Equation' for Module clock Device U2 - Reduced Equation': clk :- !(elk); re,yne :- !(!elk • Ire, , elk • !resync); reseth .- !(!elk !re5Ync' elk 6 !reseth); re,etl .- !(re,eth); t e l ' !elk , tel :- !lelk teO teO :- !(elk teO' !elk , teout !tel , !teO , !te1); !teO); :- !(!tcod , !tload , teout 6 tload , elk. tload , !teO 6 tload !t e 1 , t loa d refreq'tloed); tload .
DRAM PLD Descriptions B
APPENDIX B DRAM PLD DESCRIPTIONS This section describes the inputs, outputs, and functions of each of the PLDs in the DRAM design described in Chapter 6. The terms Start-Of-Phase and Middle-Of-Phase used to describe PLD input sampling times refer to the Intel386 DX microprocessor internal CLK phase and are defined in Figure B-lo The setup, hold, and propagation delay times for each PLD input and output can be determined from the PLD data sheets.
DRAM PLD DESCRIPTIONS module DRAM_CONTROLLER_FOR_80386 flag '-r3','-t2 title '80386 Interleaved DRAM Controller pal-t plpellned lws' U33 device 'P20R8'; U " Constants: ON OFF o; h I o; 1; 1; " ABEL 'don't care' symbol " ABEL 'clacking Input' symbol • X• ; • C• ; "Pin names: "Control pin 1; "81il386 Double-Frequency system clock pin 13; "Output Enable (tie active law> c lk 2 oe "Inputs pc lk ads mlo pa2 Iready r a sOp 5e 11 raslp ref I n res e t s e 12 pin pin pin pin pin pin pin pin pin pin pi
DRAM PLD DESCRIPTIONS "bu. cycle tracking state.dlagr.m [bu,cyc,pipecycl .tate [1,11: "Idle if (!ad, I pclk) then [0,11 e I ,e [1, 1 1 ; ,tate [0,11: ".ctlve if (Iready I .d. I pclk) the n [1, 1 1 pclk) then [1,01 el,e If (Iready I !.d. el.e [0,11; ,tate [1,01: "plpelined if (pclk> then [0,11 e I ,e [1, 0 1 ; st.te [0,01: "Illegal got a [1, 1 1 ; ""II"llllt,"""""IIIIIIIIII"""IIII""II"IIIIIIIIII"II"1111""IIIIUIIHIIII"'IIIIIIIIIIIII"IIII"II"II"" start.diagram [dram,tart,rowsell; .
DRAM PLD DESCRIPTIONS ,tate.dlagram [ra,l]; ~tate ra,lld]e: "walt fpr DRAM ar refre.h cycle, If (pclk , !ads , mia' .elecl • !muxae , pa2 , raslp & !refln) then raslaet e15e If(pcH & ,.Ieet & mla & !muxae , pa2 I r •• lp & !buHyc !refln & ! Iready} then rasl.ct el.e If (pclk & muxae & !refadrae) Ihen ra,lacl el,e ra.lldle; ,tate raslacl: "a.5ert ras far bank If (pelk I re5et> lhen r.,lldle else If (pclk Ire.dy) then ra,lldle else If (pclk , muxae , refadrae) Ihen el5e ra,lacl; r.
DRAM PLD DESCRIPTIONS [c,h,l,h,h,h,h,l,h,h,l,ll [c,l,x,h,h,h,h,l,h,x,l,ll [c,h,h,h,h,h,h,h,l,l,l,ll [ c , I , h , h ,'h , h , h , h , I , I , I , I I [c,h,h,h,h,h,h,h,I,I,I,11 [c, I , x , h , x ,h , h ,h , I , x , I , I I -+ -+ -+ -+ -+ -+ [ I ,h, [ I ,h , [h, h , [h, h, [h , h , [h, h, 1 ,h, I, I , I ,I , I ,I , I ,h, I ,h, [c,h,I,h,h,h,h,h,I,h,I,ll [c,I,x,h,h,h,h,h,I,x,I,ll [c,h,l,h,h,h,h,h,l,l,l,ll [c,I,x,h,h,h,h,h,I,I,I,11 -+ -+ -+ -+ [h,h,h,h,I,hl; [h,h,h,h,I,hl; [h,h,h,h,I,hl; [h,h,h,h,I,hl; [
DRAM PLD DESCRIPTIONS Device U33 - Reduced Equations: buscyc :" !(bU5CYC , pclk • !plpecyc , !buscyc • !pclk , plpecyc , !buscyc • !Iready , plpecyc , !ads , bU5CyC , pclk); plpecyc :" !(buscyc' !pclk' !plpecyc , !ads , !buscyc , Iready , pclk , plpecycl; dramstart :" !C!dramshrt , !pclk , !dramstart , rowsel , !buscyc , !Iready , miD' !mUXDe , pclt , rasOp , raslp , !refln • rDws~1 , sell' sel2 , lads , miD' !mUXDe , pa2 , pclk , raslp , !refln , rDwsel , sell' sel2 , lads , miD' !mUXDe , !pa2 , pclt , ra
DRAM PLD DESCRIPTIONS module flag '-r3' 1'~~2' ,'-ul' title '80386 Interleaved DRAM Controller pld-2 pipelined 1ws Intel Corporation.' U34 'E~32~'; device " Constants: ON OFF 1; 0; h 1 1; 0; x c .x. ; " ABEL 'don't care' symbol " ABEL 'clocking input' symbol .C.
DRAM PLD DESCRIPTIONS state_diagram [refin,qr]; state [0,1]: "idle if (refreq & pclk) then [1,1] else [0,1]; state [1,1]: " request refresh if (pclk & reset) then [0,1] else if ( !rasO & !rasl & pclk ) then [0,0] else [1,1]; state [0,0]: " wait for request to be negated if (pclk & reset) then [0,1] else if ( !refreq & pclk) then [0,1] else [0,0]; state [1,0]: " illegal goto [0,1]; state_diagram [rasOp]; state 1: if (pclk & !rasO) then 0 else 1; state 0: if (pclk & rasO) then 1 else 0; state_diagram [raslp]
infel® DRAM PLD DESCRIPTIONS state_diagram [cas,ale]; state [1,1]: if (pclk & !rasO & ras1 & !w_r) then [0,0] else if (pclk & rasO & !ras1 & !w_r) then [0,0] else if (pclk & !rasO & ras1 & w_r) then [1,0) else if (pclk & rasO & !ras1 & w_r) then [1,0) else [1,1); state [1,0]: gete n wait fer valid write data [0,0]; state [0,0]: if (reset & pclk) then [1,1] else if (pclk & !dramrdy) then [1,1] else [0,0]; state [0,1): "invalid state gote [1,1]; Figure B-3. DRAMP2 PLD Equations (Contd.
I"n+'eII ® DRAM PLD DESCRIPTIONS ([clk2,pclk,w_r,dramstart,rasO,rasl,muxoe,refreq,reset] -> test _vectors [cas,rasOp,raslp,dramrdy,refin,we]l; "c p 1t1 c "k 1 w "2 k r [c,h,l, [c,l,l, [c, h, 1, [c, 1, 1, [c, h, 1, [c,l,l, [c,h,l, [c,l,l, [c,h,l, [c,l,l, r d m e r r a r r u f e m a a x r S s s s 0 e e t 0 1 e q t h,h,h ,x ,h ,h h,h,h ,x ,h ,h h,h,h ,1 ,1 ,1 x,x,h ,1 ,1 ,1 l,l,h ,1 ,I ,1 l,l,h ,1 ,1 ,1 h,l,h ,1 ,1 ,1 h,l,h ,1 ,1 ,1 h,l,h ,1 ,1 ,1 h,l,h ,I ,I ,I r r r r a a e e c s s a f a 0 1 d i w s p
DRAM PLD DESCRIPTIONS 80386 Interleaved DRAM Controller pld-l pipelined lws Equations for Module DRAM_CONTROLLER_FOR_80386 Device U34 - Reduced Equations: !refin := (!refin & !refreq !qr pclk & !rasO & !rasl & refin pclk & refin & reset !pclk & !refin); ** * * (!pclk & !qr & !refin !qr & !refin & refreq & !reset pclk & qr & !rasO & !rasl & refin & !reset); !qr * * * pclk ! rasO) ; !raslp (!pclk & !raslp * pclk & !rasl); !we (dramstart & !we * pclk & !we * !dramstart & !pclk & w_r); !dramrdy (!dramrdy
DRAM PLD DESCRIPTIONS REFRESH ADDRESS COUNTER PLD The Refresh Address Counter PLD maintains the address of the next DRAM row to be refreshed. After every refresh cycle, the PLD increments this address. Table B-1 shows the inputs and outputs of the Refresh Address Counter PLD. PLD equations are shown in Figure B-4. Ten bits of row address are provided using a 20RSlO PLD. For a system operating at any speed, standard-PLD speeds are sufficient. Table 8-1.
DRAM PLD DESCRIPTIONS module rehddr; flag '-r3'; title 'refresh address counter pal HDM Intel corporation' "Increments the addr~ss b, one until 9 bits are 01FFH U3S device 'p20rsl0'; h,l,c , ! " 1,0,.C.,.x.
I"n+'e-I ® DRAM PLD DESCRIPTIONS state_dl~gram [RASI state [01: If (RA4 RA3' RA2 , e 15e [0 I ; state [11: If (RA4 , RA3 , RA2 , e I s e [1 I ; RAl , RAO) then 1 RAl , RAO) then [01 5t~te_dlagr~m [RAGI state [01: If (RAS e I s e [0 state [11: If (RAS e I s e [1 , RA4 , I; , RA4 , RA3 & RA2 & RAl &RAO) then RA3 & RA2 , , if RAO) RAO) then (RA7 RAO) then [01 I; state_diagram [RA71 state [01: RAS , RA4 , If (RAG else [0]; state [11: If (RAG' RAS & RA4 , e I s e [1 I ; state_dlaQram
DRAM PLD DESCRIPTIONS refresh address counter pal Equations for Module refaddr intel corporation Device U3S - Reduced Equations: RAO :" !CRAO); RA1 :, !CRAO & RA1 # RA1 & RA2 !RAO & , !RA1); !RAO RA2 :" !(RAO RA3 : ' ! ( RA 0 & !RAO ! RA 1 I ! RA 2 RA 1 & RA2 & !RA3 & ! RA3 & !RA3); RA3 RA4 :' ,, ,, : . ! ( RA 0 , ! RA 0 , ! RA 1 !RA2 ! RA3 , !RA4 : .
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