Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family Specification Update December 2013 Revision 007 Reference Number: 328899-007
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Contents Contents Revision History ...............................................................................................................5 Preface ..............................................................................................................................6 Summary Tables of Changes ..........................................................................................8 Identification Information ...............................................................................
Contents 4 Specification Update
Revision History Revision 001 002 Description • Initial Release. • No Updates. Revision number added to Revision History to maintain consistency with NDA Specification Update numbering. • Errata — Added HSD59-99 Updated Identification Information 003 • 004 Specification Update N/A August 2013 No Updates. Revision number added to Revision History to maintain consistency with NDA Specification Update numbering.
Preface This document is an update to the specifications contained in the Affected Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents.
Nomenclature Errata are design defects or errors. These may cause the processor behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics such as, core speed, L2 cache size, package type, etc.
Summary Tables of Changes The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. These tables uses the following notations. Codes Used in Summary Tables Stepping X: Errata exists in the stepping indicated.
Errata (Sheet 1 of 5) Steppings Number Status ERRATA C-0 Specification Update HSD1 X No Fix LBR, BTS, BTM May Report a Wrong Address when an Exception/ Interrupt Occurs in 64-bit Mode HSD2 X No Fix EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a Translation Change HSD3 X No Fix MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB Error HSD4 X No Fix LER MSRs May Be Unreliable HSD5 X No Fix MONITOR or CLFLUSH on the Local XAPIC's Addre
Errata (Sheet 2 of 5) Steppings Number Status ERRATA C-0 10 HSD26 X No Fix Specific Graphics Blitter Instructions May Result in Unpredictable Graphics Controller Behavior HSD27 X No Fix Processor May Enter Shutdown Unexpectedly on a Second Uncorrectable Error HSD28 X No Fix Modified Compliance Patterns for 2.
Errata (Sheet 3 of 5) Steppings Number Status ERRATA C-0 Specification Update HSD55 X No Fix Internal Parity Errors May Incorrectly Report Overflow in The IA32_MCi_STATUS MSR HSD56 X No Fix Performance Monitor Events OTHER_ASSISTS.AVX_TO_SSE And OTHER_ASSISTS.SSE_TO_AVX May Over Count HSD57 X No Fix Processor May Run at Incorrect P-State HSD58 X No Fix Performance Monitor Event DSB2MITE_SWITCHES.
Errata (Sheet 4 of 5) Steppings Number Status ERRATA C-0 12 HSD82 X No Fix PCIe* Host Bridge DID May Be Incorrect HSD83 X No Fix Transactional Abort May Produce an Incorrect Branch Record HSD84 X No Fix SMRAM State-Save Area Above the 4GB Boundary May Cause Unpredictable System Behavior HSD85 X No Fix DMA Remapping Faults for the Graphics VT-d Unit May Not Properly Report Type of Faulted Request HSD86 X No Fix AVX Gather Instructions Page Faults May Report an Incorrect Faulting Addre
Errata (Sheet 5 of 5) Steppings Number Status ERRATA C-0 HSD110 X No Fix A PEBS Record May Contain Processor State for an Unexpected Instruction HSD111 X No Fix MSR_PP1_ENERGY_STATUS Reports Incorrect Energy Data HSD112 X No Fix x87 FPU DP May be Incorrect After Instructions That Save FP State to Memory HSD113 X No Fix Processor May Hang During Package C7 Exit HSD114 X No Fix Intel® TSX Instructions May Cause Unpredictable System behavior HSD115 X No Fix Spurious LLC Machine Che
Identification Information Component Identification using Programming Interface The processor stepping can be identified by the following register contents. Table 1. Reserved Desktop 4th Generation Intel® Core™ Processor Family Component Identification Extended Model Reserved Processor Type 27:20 19:16 15:14 13:12 11:8 7:4 3:0 00000000b 0011b 00b 0110b 1100b xxxxb Extended Family 31:28 Family Code Model Number Stepping ID Notes: 1. 2. 3. 4. 5.
Component Marking Information The processor stepping can be identified by the following component markings. Figure 1. Desktop 4th Generation Intel® Core™ Processor Family Top-Side Markings Table 2. Desktop Processor Identification (Sheet 1 of 2) S-Spec Number Processor Number SR147 I7-4770K Stepping Cache Size (MB) Functional Core Integrated Graphics Cores Max Turbo Freq. Rate (GHz) Memory (MHz) Core Freq. (GHz) Thermal Design Power (W) C-0 8 4 2 3.9 1600 3.
Table 2. Desktop Processor Identification (Sheet 2 of 2) Stepping Cache Size (MB) Functional Core Integrated Graphics Cores Max Turbo Freq. Rate (GHz) Memory (MHz) Core Freq. (GHz) Thermal Design Power (W) I7-4770R C-0 6 4 3 3.9 1600 3.2 65 SR18M I5-4670R C-0 4 4 3 3.7 1600 3 65 S-Spec Number Processor Number SR18K SR18Q I5-4570R C-0 4 4 3 3.2 1600 2.7 65 SR1BW I7-4771 C-0 8 4 2 3.9 1600 3.5 95 SR1CA I5-4570T C-0 4 2 2 3.6 1600 2.
Errata HSD1. LBR, BTS, BTM May Report a Wrong Address when an Exception/ Interrupt Occurs in 64-bit Mode Problem: An exception/interrupt event should be transparent to the LBR (Last Branch Record), BTS (Branch Trace Store) and BTM (Branch Trace Message) mechanisms.
HSD4. LER MSRs May Be Unreliable Problem: Due to certain internal processor events, updates to the LER (Last Exception Record) MSRs, MSR_LER_FROM_LIP (1DDH) and MSR_LER_TO_LIP (1DEH), may happen when no update was expected. Implication: The values of the LER MSRs may be unreliable. Workaround: None identified. Status: For the steppings affected, see the Summary Table of Changes. HSD5.
HSD8. FREEZE_WHILE_SMM Does Not Prevent Event From Pending PEBS During SMM Problem: In general, a PEBS record should be generated on the first count of the event after the counter has overflowed. However, IA32_DEBUGCTL_MSR.FREEZE_WHILE_SMM (MSR 1D9H, bit [14]) prevents performance counters from counting during SMM (System Management Mode). Due to this erratum, if 1. A performance counter overflowed before an SMI 2.
HSD11. Performance Monitor Precise Instruction Retired Event May Present Wrong Indications Problem: When the PDIR (Precise Distribution for Instructions Retired) mechanism is activated (INST_RETIRED.
HSD14. Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value for VEX.vvvv May Produce a #NM Exception Problem: The VAESIMC and VAESKEYGENASSIST instructions should produce a #UD (InvalidOpcode) exception if the value of the vvvv field in the VEX prefix is not 1111b. Due to this erratum, if CR0.TS is “1”, the processor may instead produce a #NM (Device-NotAvailable) exception. Implication: Due to this erratum, some undefined instruction encodings may produce a #NM instead of a #UD exception.
HSD17. PCIe* Root-port Initiated Compliance State Transmitter Equalization Settings May be Incorrect Problem: If the processor is directed to enter PCIe Polling.Compliance at 5.0 GT/s or 8.0 GT/s transfer rates, it should use the Link Control 2 Compliance Preset/De-emphasis field (bits [15:12]) to determine the correct de-emphasis level. Due to this erratum, when the processor is directed to enter Polling.Compliance from 2.5 GT/s transfer rate, it retains 2.5 GT/s de-emphasis values.
HSD21. PCIe Root Port May Not Initiate Link Speed Change Problem: The PCIe Base specification requires the upstream component to maintain the PCIe link at the target link speed or the highest speed supported by both components on the link, whichever is lower. PCIe root port will not initiate the link speed change without being triggered by the software when the root port maximum link speed is configured to be 5.0 GT/s. System BIOS will trigger the link speed change under normal boot scenarios.
HSD24. VEX.L is Not Ignored with VCVT*2SI Instructions Problem: The VEX.L bit should be ignored for the VCVTSS2SI, VCVTSD2SI, VCVTTSS2SI, and VCVTTSD2SI instructions, however due to this erratum the VEX.L bit is not ignored and will cause a #UD. Implication: Unexpected #UDs will be seen when the VEX.L bit is set to 1 with VCVTSS2SI, VCVTSD2SI, VCVTTSS2SI, and VCVTTSD2SI instructions. Workaround: Software should ensure that the VEX.L bit is set to 0 for all scalar instructions.
HSD28. Modified Compliance Patterns for 2.5 GT/s and 5 GT/s Transfer Rates Do Not Follow PCIe* Specification Problem: The PCIe controller does not produce the PCIe specification defined sequence for the Modified Compliance Pattern at 2.5 GT/s and 5 GT/s transfer rates. This erratum is not seen at 8 GT/s transfer rates. Implication: Normal PCIe operation is unaffected by this erratum. Workaround: None identified. Status: For the steppings affected, see the Summary Table of Changes. HSD29.
HSD31. MSR_PERF_STATUS May Report an Incorrect Core Voltage Problem: The core operating voltage can be determined by dividing MSR_PERF_STATUS MSR (198H) bits [47:32] by 2^13. However, due to this erratum, this calculation may report half the actual core voltage. Implication: The core operating voltage may be reported incorrectly. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Table of Changes. HSD32.
HSD35. PLATFORM_POWER_LIMIT MSR Not Visible Problem: The PLATFORM_POWER_LIMIT MSR (615H) is used to control the PL3 (power limit 3) mechanism of the processor. Due to this erratum, this MSR is not visible to software. Implication: Software is unable to read or write the PLATFORM_POWER_LIMIT MSR. If software attempts to access this MSR, a general protection fault will occur. Workaround: It is possible for the BIOS to contain a workaround for this erratum.
HSD40. Spurious VT-d Interrupts May Occur When the PFO Bit is Set Problem: When the PFO (Primary Fault Overflow) field (bit [0] in the VT-d FSTS [Fault Status] register) is set to 1, further faults should not generate an interrupt. Due to this erratum, further interrupts may still occur. Implication: Unexpected Invalidation Queue Error interrupts may occur. Intel has not observed this erratum with any commercially available software.
HSD44. Display May Flicker When Package C-States Are Enabled Problem: When package C-States are enabled, the display may not be refreshed at the correct rate. Implication: When this erratum occurs, the user may observe flickering on the display. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Table of Changes. HSD45.
HSD49. AVX Gather Instruction That Should Result in #DF May Cause Unexpected System Behavior Problem: Due to this erratum, an execution of a 128-bit AVX gather instruction may fail to generate a #DF (double fault) when expected. Instructions impacted by this erratum are: VGATHERDPS, VGATHERDPD, VGATHERQPS, VGATHERQPD, VPGATHERDD, VPGATHERDQ, VPGATHERQD, and VPGATHERQQ. Implication: When this erratum occurs, an operation which should cause a #DF may result in unexpected system behavior.
HSD53. The From-IP for Branch Tracing May be Incorrect Problem: BTM (Branch Trace Message) and BTS (Branch Trace Store) report the “From-IP” indicating the source address of the branch instruction. Due to this erratum, BTM and BTS may repeat the “From-IP” value previously reported. The “To-IP” value is not affected. Implication: Using BTM or BTS reports to reconstruct program execution may be unreliable. Workaround: It is possible for the BIOS to contain a workaround for this erratum.
HSD58. Performance Monitor Event DSB2MITE_SWITCHES.COUNT May Over Count Problem: The Performance Monitor Event DSB2MITE_SWITCHES.COUNT (Event ABH; Umask 01H) should count the number of DSB (Decode Stream Buffer) to MITE (Macro Instruction Translation Engine) switches. Due to this erratum, the DSB2MITE_SWITCHES.COUNT event will count speculative switches and cause the count to be higher than expected. Implication: The Performance Monitor Event DSB2MITE_SWITCHES.
HSD62. Some Performance Monitor Event Counts May be Inaccurate During SMT Mode Problem: The performance monitor event OFFCORE_REQUESTS_OUTSTANDING (Event 60H, any Umask Value) should count the number of occurrences that loads or stores stay in the super queue each cycle. The performance monitor event CYCLE_ACTIVITY.CYCLES_L2_PENDING (Event A3H, Umask 01H) should count the number of cycles that demand loads stay in the super queue.
HSD66. A PCIe* LTR Update Message May Cause The Processor to Hang Problem: If a PCIe device sends an LTR (Latency Tolerance Report) update message while the processor is in a package C6 or deeper, the processor may hang. Implication: Due to this Erratum the processor may hang if a PCIe LTR update message is received while in a Package C6 or deeper. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Table of Changes.
HSD70. IA32_VMX_VMCS_ENUM MSR (48AH) Does Not Properly Report The Highest Index Value Used For VMCS Encoding Problem: IA32_VMX_VMCS_ENUM MSR (48AH) bits 9:1 report the highest index value used for any VMCS encoding. Due to this erratum, the value 21 is returned in bits 9:1 although there is a VMCS field whose encoding uses the index value 23. Implication: Software that uses the value reported in IA32_VMX_VMCS_ENUM[9:1] to read and write all VMCS fields may omit one field.
Status: For the steppings affected, see the Summary Table of Changes. HSD74. Performance Monitoring Events May Report Incorrect Number of Load Hits or Misses to LLC Problem: The following performance monitor events should count the numbers of loads hitting or missing LLC. However due to this erratum, The L3_hit related events may over count and the L3_miss related events may undercount. MEM_LOAD_RETIRED.L3_HIT (Event D1H, Umask 40H) MEM_LOAD_RETIRED.
HSD78. Certain Performance Monitoring Events May Over Count Software Demand Loads Problem: The following performance monitor events should count the number of software demand loads. However due to this erratum, they may also include requests from the Next Page Prefetcher and over count. OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA (Event 60H; Umask 01H) OFFCORE_REQUESTS.DEMAND_DATA (Event B0H; Umask 01H) CYCLE_ACTIVITY.L2_Pending (Event A3H; Umask 01H) L2_HIT_MISS.
HSD82. PCIe* Host Bridge DID May Be Incorrect Problem: The PCIe Host Bridge DID register (Bus 0; Device 0; Function 0; Offset 2H) contents may be incorrect. Implication: Software that depends on the Host Bridge DID value may not behave as expected. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Table of Changes. HSD83.
HSD87. Intel® TSX Instructions May Cause Unpredictable System behavior Problem: Under certain system conditions, Intel TSX (Transactional Synchronization Extensions) instructions may result in unpredictable system behavior. Implication: Due to this erratum, use of Intel TSX may result in unpredictable behavior. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Table of Changes. HSD88.
HSD92. Execution of FXSAVE or FXRSTOR With the VEX Prefix May Produce a #NM Exception Problem: Attempt to use FXSAVE or FXRSTOR with a VEX prefix should produce a #UD (InvalidOpcode) exception. If either the TS or EM flag bits in CR0 are set, a #NM (device-notavailable) exception will be raised instead of #UD exception. Implication: Due to this erratum a #NM exception may be signaled instead of a #UD exception on an FXSAVE or an FXRSTOR with a VEX prefix.
HSD97. Video/Audio Distortion May Occur Problem: Due to this erratum, internal processor operations can occasionally delay the completion of memory read requests enough to cause video or audio streaming underrun. Implication: Visible artifacts such as flickering on a video device or glitches on audio may occur. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Table of Changes. HSD98.
HSD101. Incorrect LBR Source Address May be Reported For a Transactional Abort Problem: If the fetch of an instruction in a transactional region causes a fault, a transactional abort occurs. If LBRs are enabled, the source address recorded for such a transactional abort is the address of the instruction being fetched.
HSD105. Warm Reset Does Not Stop GT Power Draw Problem: Due to this erratum, if GT is enabled prior to a warm reset, it will remain powered after the warm reset. The processor will make incorrect power management decisions because it assumes the GT is not drawing power after a warm reset. Implication: The processor may draw more current than expected from an external VR (Voltage Regulator).
HSD109. Processor Energy Policy Selection May Not Work as Expected Problem: When the IA32_ENERGY_PERF_BIAS MSR (1B0H) is set to a value of 4 or more, the processor will try to increase the energy efficiency of Turbo mode. However, this functionality is effectively disabled if the software requested P-state exceeds the maximum P-state supported by the processer. This has the effect of decreasing the energy efficiency of the processor while in Turbo mode.
HSD113. Processor May Hang During Package C7 Exit Problem: Under certain internal timing conditions, the processor might not properly exit package C7 leading to a hang. Implication: Due to this erratum, the package C7 state may not be reliable. Intel has not observed this erratum with any commercially available system. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Table of Changes. HSD114.
The page fault (in #4) may report an incorrect error code and faulting linear address; these would describe the read-modify-write instruction’s memory access instead of that of the faulting instruction. (The address of the faulting instruction is reported correctly.) Implication: The erratum makes it appear that the page fault resulted from an access that occurred prior to the faulting instruction.
Specification Changes The Specification Changes listed in this section apply to the following documents: • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set Reference Manual A-M • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B: Instruction Set Reference Manual N-Z • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A: System P
Specification Clarifications The Specification Clarifications listed in this section may apply to the following documents: • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set Reference Manual A-M • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B: Instruction Set Reference Manual N-Z • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volu
Documentation Changes The Documentation Changes listed in this section apply to the following documents: • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set Reference Manual A-M • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B: Instruction Set Reference Manual N-Z • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A: System P
Display Family Display Model Display Family Display Model Display Family Display Model Display Family Display Model 0F_xx 06_1C 06_1A 06_1E 06_1F 06_25 06_26 06_27 06_2C 06_2E 06_2F 06_35 06_36 §§ 50 Specification Update