User’s Manual ECB-865 Intel 815E Tualatin Pentium III / Celeron Full-size CPU Card 1st Ed. – 7 February 2002 Part No.
ECB-865 FCC STATEMENT THIS DEVICE COMPLIES WITH PART 15 FCC RULES. OPERATION IS SUBJECT TO THE FOLLOWING TWO CONDITIONS: (1) THIS DEVICE MAY NOT CAUSE HARMFUL INTERFERENCE. (2) THIS DEVICE MUST ACCEPT ANY INTERFERENCE RECEIVED INCLUDING OPERATION. INTERFERENCE THAT MAY CAUSE UNDESIRED THIS EQUIPMENT HAS BEEN TESTED AND FOUND TO COMPLY WITH THE LIMITS FOR A CLASS "A" DIGITAL DEVICE, PURSUANT TO PART 15 OF THE FCC RULES.
User’s Manual Copyright Notice Copyright 2000, 2001, Evalue Technology Inc., ALL RIGHTS RESERVED. No part of this document may be reproduced, copied, translated, or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the prior written permission of the original manufacturer. Trademark Acknowledgement Brand and product names are trademarks or registered trademarks of their respective owners. Disclaimer Evalue Technology Inc.
ECB-865 A Message to the Customer Evalue Customer Services Each and every Evalue’s product is built to the most exacting specifications to ensure reliable performance in the harsh and demanding conditions typical of industrial environments. Whether your new Evalue device is destined for the laboratory or the factory floor, you can be assured that your product will provide the reliability and ease of operation for which the name Evalue has come to be known. Your satisfaction is our primary concern.
User’s Manual Product Warranty Evalue warrants to you, the original purchaser, that each of its products will be free from defects in materials and workmanship for two years from the date of purchase. This warranty does not apply to any products which have been repaired or altered by persons other than repair personnel authorized by Evalue, or which have been subject to misuse, abuse, accident or improper installation.
ECB-865 Packing List Before you begin installing your single board, please make sure that the following materials have been shipped: 1 ECB-865 Full-size Celeron / Pentium III single board 1 Quick Installation Guide 1 CD-ROM contains the followings: — User’s Manual (this manual in PDF file) — Ethernet driver and utilities — VGA drivers and utilities — Latest BIOS (as of the CD-ROM was made) Cable set includes the followings: — 1 IDE HDD cable (40-pin, pitch 2.
User’s Manual 1. MANUAL OBJECTIVES .............................................................................................1 2. INTRODUCTION.........................................................................................................2 2.1 System Overview ...................................................................................................2 2.2 System Specifications ...........................................................................................3 2.
ECB-865 3.10 Setting Jumpers ...................................................................................................20 3.10.1 3.10.2 3.10.3 3.10.4 3.10.5 Clear CMOS (JP9) ..................................................................................................... 21 Watchdog Timer ........................................................................................................ 21 COM2 RS-232/422/485 Select (JP1, JP2~JP5) .........................................................
User’s Manual 4.2 AMI BIOS Setup Main Menu ................................................................................51 4.3 CMOS Setup Reference Table.............................................................................52 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.4 5. Flash BIOS Utility .................................................................................................68 DRIVER INSTALLATION...................................................................................
ECB-865 Document Amendment History Revision 1st Date Feb. 02. Evalue Technology Inc.
ECB-865 1. Manual Objectives This manual describes in detail the Evalue Technology ECB-865 Single Board. We have tried to include as much information as possible but we have not duplicated information that is provided in the standard IBM Technical References, unless it proved to be necessary to aid in the understanding of this board. The manual is sectioned and includes a User’s Guide that will help the non-technical user to get the unit up and running.
User’s Manual 2. 2.1 Introduction System Overview The ECB-865 is an all-in-one Full-size Pentium III / Celeron Single Board Computer (SBC) designed with Intel embedded chipset 815E-B which supports the latest Intel FC-PGA/FCPGA2 Pentium III / Celeron processor (CopperMine and Tualatin) up to 1.1GHz or above and AGP 4X 3D Graphics Accelerator w/ shared display memory of 4MB SDRAM, dual Intel PCI-bus Fast Ethernet controllers, and M-Systems DiskOnChip socket.
ECB-865 2.2 System Specifications General Functions • Bus Interface: PICMG 2.0 Compliant • ISA Driving Capacity: Built-in Address/Data buffer supports driving capacity up to 64mA • CPU: Supports Intel FCPGA/FCPGA2 Pentium III / Celeron processor up to 1GHz or above (with system bus frequencies of 66/100/133MHz) • CPU Socket: Intel FC Socket 370 • BIOS: AMI 4Mb FWH BIOS • Chipset: Intel 815E-B AGPset • I/O Chipset: ITE IT8712F-A • Memory: Onboard three 168-pin DIMM sockets support up to 1.
User’s Manual • Interrupt: 15 interrupt levels (8259 equivalent) • Hardware Status Monitoring: Monitoring system temperature, voltage, and cooling fan status. Auto throttling control when CPU overheats • Power Management: Supports ATX power supply. Supports PC98, LAN wake up and modem ring-in functions. I/O peripheral devices support power saving and doze/standby/suspend modes. APM 1.
ECB-865 Mechanical and Environmental • Power Supply Voltage: +5V (4.75V to 5.25V), +12V (11.4V to 12.6V), and -12V (11.4V to -12.6V) • Typical Power Requirement: +5V @ 6.5A, +12V @ 140mA, -12V @ 30mA w/ Intel Celeron 466MHz CPU and 128MB SDRAM • Operating Temperature: 32 to 140 °F (0 to 60 °C) • Board Size: 13.3"(L) x 4.8"(W) (338mm x 122mm) • Weight: 0.
User’s Manual 2.3 Architecture Overview The following block diagram shows the architecture and main components of ECB-865. Two major chipsets on board are the 82815E Graph Memory Control Hub and 82801BA ICH2. These two devices provide interface to Socket370 processor, supports CRT display, SDRAM with ECC, PCI bus interface, ACPI compliant power management , USB port, SMBus communication, and Ultra DMA/33/66/100 IDE Bus Master.
ECB-865 2.3.1 82815 GMCH and 82801BA The Intel® 815 chipset for use with the universal socket 370 is a high-flexibility chipset designed to extend from the basic graphics/multimedia PC platform up to the mainstream performance desktop platform. The chipset consists of the Intel_ 82815 Graphics and Memory Controller Hub (GMCH) and an I/O Controller Hub (ICH or ICH2) for the I/O subsystem. The GMCH integrates a system memory SDRAM controller that supports a 64-bit 100/133 MHz SDRAM array.
User’s Manual 2.3.2 DRAM Interface The GMCH integrates a system memory controller that supports a 64-bit 100/133 MHz SDRAM array. The only DRAM type supported is industry standard Synchronous DRAM (SDRAM). The SDRAM controller interface is fully configurable through a set of control registers.
ECB-865 2.3.4 PCI Interface The ICH2 PCI interface provides a 33 MHz, Rev. 2.2 compliant implementation. All PCI signals are 5V tolerant, except PME#. The ICH2 integrates a PCI arbiter that supports up to six external PCI bus masters in addition to the internal ICH2 requests. 2.3.5 IDE Interface (Bus Master Capability and Synchronous DMA Mode) The fast IDE interface supports up to four IDE devices providing an interface for IDE hard disks and CD ROMs. Each IDE device can have independent timings.
User’s Manual 2.3.7.2 Intel 82559 The Ethernet interface is based on an Intel 82559 Ethernet controller that supports both 10BASE-T and 100BASE-TX. The 82559 consists of both the Media Access Controller (MAC) and the physical layer (PHY) interface combined into a single component solution. The 32-bit PCI controller provides enhanced scatter-gather bus mastering capabilities and enables the 82559 to perform high speed data transfers over the PCI bus.
ECB-865 3. Hardware Configuration This chapter explains you the instructions of how to set up your system. The additional information shows you how to install M-Systems’ DiskOnChip and program the Watchdog Timer. 3.1 Installation Procedure 1. Turn off the power supply. 2. Insert the DIMM module (be careful with the orientation). 3. Insert all external cables for hard disk, floppy, keyboard, mouse, USB etc. except for flat panel.
User’s Manual 3.3 Socket 370 Processor 3.3.1 Installing Celeron / Pentium III (Coppermine/Tualatin) CPU Lift the handling lever of CPU socket outwards and upwards to the other end. Align the processor pins with pin holes on the socket. Make sure that the notched corner or dot mark (pin 1) of the CPU corresponds to the socket’s bevel end. Then press the CPU gently until it fits into place. If this operation is not easy or smooth, don’t do it forcibly.
ECB-865 3.5 M-Systems’ DiskOnChip Flash Disk ECB-865 reserves a 32-pin DIP socket to support M-Systems’ DiskOnChip flash disk up to 288 MB. The DiskOnChip is based on pure ISA bus and without PnP (Plug and Play) function. Before the installation, make sure that the DiskOnChip I/O address jumper is set properly to prevent the I/O resource conflict. 3.5.1 Installing DOC Align the DOC with the pinholes on the socket.
User’s Manual 3.7.1 815E integrated Graphics Controller The on-board graphics controller integrated in 815E(GMCH) chipset that integrates high performance memory technology for the graphics frame buffer. 32 –bit data interface,133 Mhz SDRAM interface only.Flexible AGP in-line Memory Module (AIMM) implementation. support for two1M X16,or one 2M X32,4MB maximum addressable, thus increasing the available memory bandwidth for the graphics subsystem to support high color/high resolution application.
ECB-865 3.7.2 Intel 82559(or REALTEK RTL8139C) & 82801BA(ICH2) + 82562ET (PHY) Network Controller The 82559 (or RTL8139C) and ICH2+PHY is fully integrated 10BASE-T/100BASE-TX LAN solution. The 32-bit PCI controller provides enhanced scatter-gather bus mastering capabilities and enables the 8139C to perform high-speed data transfers over the PCI bus.
User’s Manual 3.8 Watchdog Timer Programming When the Watch-Dog Timer (WDT) function is enabled, a system reset will be generated unless an application triggers the timer periodically within time-out period. This allows the system to restart in an orderly way in case of any abnormal condition is found. An optional two-port WDT is provided on ECB-865. This WDT comes with 8 possible ranges of time intervals from 500ms to 64sec., which can be adjusted by setting jumper positions.
ECB-865 3.9 3.9.
User’s Manual 3.9.2 Jumper & Connector List Connectors on the board are linked to external devices such as hard disk drives, keyboard, mouse, or floppy drives. In addition, the board has a number of jumpers that allow you to configure your system to suit your application. The following tables list the function of each of the board's jumpers and connectors. Jumpers Label Function Note JP1 Serial port RS-232/422/485 select 3 x 2 header, pitch 2.
ECB-865 Connectors Label Function J1 System reset connector 2 x 1 header, pitch 2.54mm J2 J3 External speaker connector 4 x 1 header, pitch 2.54mm 4 x 1 header, pitch 2.54mm J5 Keyboard lock and power indicator connector Primary IDE / Secondary IDE active indicator connector Primary IDE connector J6 Floppy connector 17 x 2 header, pitch 2.54mm J7 AT power button connector J8 ATX power button interface to backplane 2 x 1 header, pitch 2.
User’s Manual 3.10 Setting Jumpers You can configure your board to match the needs of your application by setting jumpers. A jumper is the simplest kind of electric switch. It consists of two metal pins and a small metal clip (often protected by a plastic cover) that slides over the pins to connect them. To “close” a jumper you connect the pins with the clip. To “open” a jumper you remove the clip. Sometimes a jumper will have three pins, labeled 1, 2, and 3.
ECB-865 3.10.1 Clear CMOS (JP9) You can use JP9 to clear the CMOS data if necessary. To reset the CMOS data, short JP1 for just a few seconds, and then remove the jumper back to open. Clear CMOS (JP1) Protect* JP1 1 2 Clear CMOS 1 2 * default 3.10.2 3.10.2.1 Watchdog Timer Enable / Disable Onboard Watchdog Timer (JP12) You can use JP12 to enable / disable the onboard Watchdog timer function if necessary.
User’s Manual 3.10.2.3 Watchdog Timer Time-Out Interval Select (JP10) You can set JP10 to select the Watchdog timer time-out interval to be 0.5, 1, 2, 4, 8, 16, 32, or 64 Sec. Watchdog Timer Tim-Out Interval Select (JP10) 0.5 Sec. 1 Sec. * 2 Sec. JP10 4 Sec. 1 3 5 1 3 5 1 3 5 1 3 5 2 4 6 2 4 6 2 4 6 2 4 6 8 Sec. 16 Sec. 32 Sec. 64 Sec. 1 3 5 1 3 5 1 3 5 1 3 5 2 4 6 2 4 6 2 4 6 2 4 6 * default 3.10.
ECB-865 3.10.4 M-Systems DiskOnChip Memory Address Select (JP11) The M-systems DiskOnChip memory address can be selected by JP11. The choice is D0000~D1FFF, D2000~D3FFF, D4000~D5FFF, D6000~D7FFF. M-systems DiskOnChip Memory Address Select (JP11) D0000* D2000 D4000 D6000 2 4 6 8 2 4 6 8 2 4 6 8 2 4 6 8 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 JP11 * default 3.10.5 Proprietary PCI Bus Master Selection (JP13) The Proprietary PCI Bus Master is selected by JP13.
User’s Manual 3.11 3.11.1 3.11.2 3.11.3 3.11.
ECB-865 3.11.
User’s Manual 3.11.
ECB-865 3.11.7 Signal Description – Primary & Secondary IDE Connector (J5 & J10) PDA [2:0] Primary Disk Address [2:0]. These signals indicate which byte in either the ATA command block or control block is being addressed. If the IDE signals are configured for Primary and Secondary, these signals are connected to the corresponding signals on the Primary IDE connector. If the IDE signals are configured for Primary 0 and Primary 1, these signals are used for the Primary 0 connector.
User’s Manual PDIOR# Primary Disk IO Read. In normal IDE this is the command to the IDE device that it may drive data onto the PDD [15:0] lines. Data is latched by PIIX4 on the negation edge of PDIOR#. The IDE device is selected either by the ATA register file chip selects (PDCS1#, PDCS3#) and the PDA [2:0] lines, or the IDE DMA slave arbitration signals (PDDACK#). In an Ultra DMA/33 read cycle, this signal is used as DMARDY# which is negated by the PIIX4 to pause Ultra DMA/33 transfers.
ECB-865 PDIORDY Primary IO Channel Ready. In normal IDE mode, this input signal is directly driven by the corresponding IDE device IORDY signal. In an Ultra DMA/33 read cycle, this signal is used as STROBE, with the PIIX4 latching data on rising and falling edges of STROBE. In an Ultra DMA/33 write cycle, this signal is used as the DMARDY# signal which is negated by the drive to pause Ultra DMA/33 transfers.
User’s Manual SDDACK# Secondary DMA Acknowledge. This signal directly drives the IDE device DMACK# signal. It is asserted by PIIX4 to indicate to IDE DMA slave devices that a given data transfer cycle (assertion of SDIOR# or SDIOW#) is a DMA data transfer cycle. This signal is used in conjunction with the PCI bus master IDE function. It is not associated with any AT compatible DMA channel.
ECB-865 3.11.
User’s Manual 3.11.9 Signal Description – Floppy Connector (J6) RDATA# The read data input signal from the FDD. WD# Write data. This logic low open drain writes pre-compensation serial data to the selected FDD. An open drain output. WE# Write enable. An open drain output. MOA# Motor A On. When set to 0, this pin enables disk drive 0. This is an open drain output. MOB# Motor B On. When set to 0, this pin enables disk drive 1. This is an open drain output. DSA# Drive Select A.
ECB-865 3.11.10 ATX Power Button Connector (J8) Signal PIN Power Button Control Signal GND 3.11.
User’s Manual 3.11.
ECB-865 3.11.13 Signal Description – Parallel Port Connector (J11) The following signal description covers the signal definitions, when the parallel port is operated in standard centronic mode. The parallel port controller also supports the fast EPP and ECP modes. Please refer to reference 2 for further information. PD7..0 Parallel data bus from PC board to printer. The data lines are able to operate in PS/2 SLIN# Output line for detection of printer selection. This pin is pulled high internally.
User’s Manual 3.11.15 Serial Port 1 / Serial Port 2 with External DB9 Connector (J9, J12) Signal GND DTR TxD RxD DCD 3.11.16 TxD PIN Signal 5 9 RI 8 CTS 7 RTS 6 DSR 4 3 2 1 Signal Description – Serial Port 1 / Serial Port 2 in RS-232 Mode (J9, J12) Serial output. This signal sends serial data to the communication link. The signal is set to a marking state on hardware reset when the transmitter is empty or when loop mode operation is initiated. RxD Serial input.
ECB-865 3.11.17 Box Header Serial Port 1 / Serial Port 2 Connector in RS-422 (J9, J12) Signal 3.11.18 TxD +/- PIN Signal NC 10 9 RI CTS 8 7 RTS DSR 6 5 GND TxD+ 4 3 TxD- RxD- 2 1 RxD+ Signal Description – Serial Port 1 / Serial Port 2 in RS-422 Mode (J9, J12) Serial output. This differential signal pair sends serial data to the communication link.
User’s Manual 3.11.20 Signal Description – Serial Port 1 / Serial Port 2 in RS-485 Mode (J9, J12) RxD/TxD +/- Bi-directional data signal pair. Received data is available in Serial Port 2 Receiver Buffer Register. Data is transferred from Serial Port 2 Transmit Buffer Register to the communication line, if the TxD line driver is enabled through the Serial Port 2’s DTR signal (Modem control register). The data transmitted will simultaneously be received the in Serial Port 2 Receiver Buffer Register.
ECB-865 3.11.21 USB Connector (J13, J19) PIN Signal 3.11.22 D1+ / D1- CH2 CH1 Signal NC 9 10 VCC2 GND 7 8 D2- D1+ 5 6 D2+ D1- 3 4 GND VCC1 1 2 NC Signal Description – USB Connector (J13, J19) Differential bi-directional data signal for USB channel 0. Clock is transmitted along with the data using NRZI encoding. The signalling bit rate is up to 12 Mbs. D2+ / D2- Differential bi-directional data signal for USB channel 1. Clock is transmitted along with the data using NRZI encoding.
User’s Manual 3.11.25 Signal Configuration – Fast & Standard IrDA Connector (J15) IRRX Infrared Receiver input IRTX Infrared Transmitter output 3.11.26 3.11.
ECB-865 3.11.28 3.11.29 10/100 BASE-Tx Ethernet Connector (J18, J20) Signal PIN TXD+ 1 TXD- 2 RXD+ 3 NC 4 NC 5 RXD- 6 NC 7 NC 8 Signal Description – 10/100Base-Tx Ethernet Connector (J18, J20) TXD+ / TXD- Ethernet 10/100Base-Tx differential transmitter outputs. RXD+ / RXD- Ethernet 10/100Base-Tx differential receiver inputs.
User’s Manual 3.11.30 CRT Connector (J22) Signal RED PIN Signal 6 ANA-GND 1 11 7 GREEN 2 ANA-GND 12 8 BLUE 3 NC DDCDAT ANA-GND 13 HSYNC 9 NC 4 VCC 14 10 DIG-GND 3.11.31 5 VSYNC DIG-GND 15 DDCCLK Signal Description – CRT Connector (J22) HSYNC CRT horizontal synchronisation output. VSYNC CRT vertical synchronisation output. DDCCLK Display Data Channel Clock. Used as clock signal to/from monitors with DDC interface. DDCDAT Display Data Channel Data.
ECB-865 3.11.32 3.11.33 Internal Keyboard Connector (J24) Signal PIN KCLK 1 KDAT 2 NC 3 GND 4 VCC 5 PS/2 Keyboard Connector (J26) Signal PIN NC 6 5 KCLK VCC 4 3 GND NC 3.11.34 Signal 2 1 KDAT Signal Description – Int. & PS/2 Keyboard Connector (J24, J26) KCLK Bi-directional clock signal used to strobe data/commands from/to the PC-AT keyboard. KDAT Bi-directional serial data line used to transfer data from or commands to the PC-AT keyboard. 3.11.
User’s Manual 3.11.37 Proprietary PCI Connector (J21) Signal +12V +12V VSYNC GND HSYNC CLK GND REQ# AD31 AD29 DEVSEL# AD27 AD25 C/BE3# +3.3V +3.
ECB-865 3.11.38 Signal Description – Proprietary PCI Connector (J21) 3.11.38.1 Address & Data AD [31::00] Address and Data are multiplexed on the same PCI pins. A bus transaction consists of an address phase followed by one or more data phases. PCI supports both read and write bursts. The address phase is the clock cycle in which FRAME# is asserted. During the address phase AD [31::00] contain a physical address (32 bits).
User’s Manual 3.11.38.2 System CLK Clock provides timing for all transactions on PCI and is an input to every PCI device. All other PCI signals, except RST#, INTA#, INTB#, INTC#, and INTD#, are sampled on the rising edge of CLK and all other timing parameters are defined with respect to this edge. PCI operates up to 33 MHz or 66 MHz and, in general, the minimum frequency is DC (0 Hz). Reset is used to bring PCI-specific registers, sequencers, and signals to a consistent state.
ECB-865 3.11.38.3 Interface Control FRAME# Cycle Frame is driven by the current master to indicate the beginning and duration of an access. FRAME# is asserted to indicate a bus transaction is beginning. While FRAME# is asserted, data transfers continue. When FRAME# is deasserted, the transaction is in the final data phase or has completed. Initiator Ready indicates the initiating agent’s (bus master’s) ability to complete the current data phase of the transaction. IRDY# is used in conjunction with TRDY#.
User’s Manual 3.11.38.4 Arbitration REQ# Request indicates to the arbiter that this agent desires use of the bus. This is a point to point signal. Every master has its own REQ# which must be tri-stated while RST# is asserted. Grant indicates to the agent that access to the bus has been granted. This is a point to point signal. Every master has its own GNT# which must be ignored while RST# is asserted. GNT# 3.11.38.
ECB-865 3.11.38.6 Interrupts PIRQ# Interrupts on PCI are optional and defined as "level sensitive," asserted low (negative true), using open drain output drivers. The assertion and deassertion of INTx# is asynchronous to CLK. A device asserts its INTx# line when requesting attention from its device driver. Once the INTx# signal is asserted, it remains asserted until the device driver clears the pending request. When the request is cleared, the device deasserts its INTx# signal.
User’s Manual 4. AMI BIOS Setup ECB-865 is equipped with the AMI BIOS stored in Flash ROM. This BIOS has a built-in Setup program that allow users to modify the basic system configuration easily. This type of information is stored in CMOS RAM so that it is retained during power-off periods. 4.1 Entering Setup Turn on or reboot the computer. When the message ”Hit” appears if you want to run SETUP, press key immediately to enter BIOS Setup program.
ECB-865 4.2 AMI BIOS Setup Main Menu Once you enter ECB-865 AMI BIOS COMS Setup Utility, the Main Menu “Standard CMOS Setup” will appear on the screen. The Main Menu allows you to select from eleven Setup functions and two exit choices. Use arrow keys to switch the items and press key to accept or enter the sub-menu Note: It is strongly recommended to reload Optimal setting if CMOS is lost or BIOS is updated.
User’s Manual 4.3 CMOS Setup Reference Table This Setup reference table includes all the Optimal, Failsafe, and other options setting in each BIOS setup item. It is very easy to take a look for crossing reference. If you want to go details, you can directly refer to item description in sub-section. 4.3.1 Standard CMOS Setup Menu This Setup page includes all the items in standard CMOS Setup.
ECB-865 4.3.1.3 Master Disk, Slave Disk Select the appropriate values to configure the hard disk type you are using for the master and the slave. Available types are 1~46, USER, AUTO, Not Installed, and CDROM. The settings have not been preinstalled. 4.3.1.4 Boot Sector Virus Protection Enabling this option allows the system to issue a warning when any program (or virus) issues a disk format command or attempts to write to the boot sector of the hard disk drive.
User’s Manual 4.3.2 Advanced CMOS Setup Defaults This Setup includes all of the advanced features in the system. The detail descriptions are specified as below. 4.3.2.1 Quick Boot Set this option to Enabled to instruct AMIBIOS to boot quickly when the computer is powered on. Disabled: AMIBIOS tests all system memory. AMIBIOS waits up to 40seconds for a READY signal from the IDE hard disk drive. AMIBIOS waits for 0.
ECB-865 4.3.2.2 1st / 2nd / 3rd Boot Device These options determine the sequence of boot drives (floppy drive A:, hard disk drive C:, or CD-ROM drive) that the AMIBIOS attempts to boot from after AMIBIOS POST completes. 4.3.2.3 Try Other Boot Device Set this option to Yes to try other boot device. The settings are Yes or No. The default setting is Yes. 4.3.2.4 S.M.A.R.T. for Hard Disks Set this option to Enabled the S.M.A.R.T function for Hard Disks. The settings are Enabled or Disabled.
User’s Manual 4.3.2.11 Boot To OS/2 Set this option to Yes to permit AMIBIOS to run with IBM OS/2. The settings are Yes or No. The default setting is No. 4.3.2.12 System BIOS Cacheable When this option is set to Enabled, the contents of the F0000h system memory segment can be read from or written to L2 cache memory. The contents of the F0000h memory segment are always copied from the BIOS ROM to system RAM for faster execution. The settings are Enabled or Disabled. 4.3.2.
ECB-865 4.3.3 Advanced Chipset Setup Defaults This Setup is very important to keep system’s stability. If you are not technical person, do not attempt to change any parameters. The best way is to choose optimal default setting. 4.3.3.1 CPU Ratio Selection This option provides different CPU clock Ratios from 3.0x to 8.0x. When you change the ratio, the overall CPU speed will change accordingly. In the default setting of “Safe Mode”, the CPU operates its own original clock rate automatically.
User’s Manual 4.3.3.3 Memory Hole This option allows the end user to specify the location of a memory hole for memory space requirement from ISA-bus cards. 4.3.3.4 DRAM Cycle time (SCLKs) This option selects the number of SCLKs for an access cycle. 4.3.3.5 CAS# Latency (SCLKs) This option controls the number of SCLKs between the time a read command is sampled by the SDRAM and GMCH 82815E samples corresponding data from the SDRAMs. 4.3.3.
ECB-865 4.3.4 Power Management Setup Defaults This APM (Advanced Power Management) determines how much power energy setting below items to handle system power resource can save. The following descriptions will specify the definition of each item in details. 4.3.4.1 ACPI Aware O/S This item allows you to enable/disable the Advanced Configuration and Power Management (ACPI). The choice: Yes, No. 4.3.4.
User’s Manual 4.3.4.4 Stand by Time Out (Minute) This option specifies the length of the period of system inactivity while the computer is in Full-On power state before the computer is placed in Standby mode. When this length of time expires, the computer enters Standby Timeout state. In Standby mode, some power use is curtailed. 4.3.4.5 Suspend Time Out (Minute) This option is the same as Stand by Time out function.
ECB-865 4.3.4.10 Power Button Function This item is used to handle soft power on/off regardless of time counting (generally speaking, it is 4 sec) if you set it to On/Off. You can easily power on/off system by pressing power button (toggle switch) directly. This feature is only available on system with ATX power control interface. If you use standard AT power supply, this option will be ignored.
User’s Manual 4.3.5 PCI / Plug and Play Setup Defaults This section describes configuring the PCI bus system. PCI (Peripheral Component Interconnect) is a system that allows I/O devices to operate at speeds nearing CPU’s when they communicate with own special components. All of options described in this section are important and technical and it is strongly recommended that only experienced users could make any changes to the default settings. 4.3.5.
ECB-865 4.3.5.2 Clear NVRAM This option is used to clear NVRAM and check or update ESCD (Extended System Configuration Data) data after system power on. Set this option to No that will not clear NVRAM and the operation of update ESCD is effective in different ESCD data comparison. If you select the “Yes” setting, then the BIOS will update ESCD each time of power on. 4.3.5.3 PCI Latency Timer (PCI Clocks) This option sets the latency of all PCI devices on the PCI bus.
User’s Manual 4.3.6 Peripheral Setup Defaults This section describes I/O resources assignment for all of on-board peripheral devices. 4.3.6.1 OnBoard FDC This option enables the floppy drive controller onboard. The settings are Auto, Enabled, or Disabled. 4.3.6.2 OnBoard Serial Port1 This option enables serial port 1 onboard and specifies the base I/O port address for serial port 1. The settings are Auto, Disabled, 3F8h, 3E8h, 2E8h, and 2F8h. The Fail-Safe default setting is Auto. 4.3.6.
ECB-865 4.3.6.4 On Board Parallel Port There are four optional items Parallel Port Mode, EPP Version, Parallel Port IRQ, and Parallel Port DMA Channel used to control on-board parallel port interface while user select I/O base address manually. The following lists are available options of on-board parallel port: Disabled on-board parallel port function is ineffective and N/A 378h locate IRQ7 for this default I/O address 278h assign this I/O address to LPT1 3BCh assign this I/O address to LPT1 4.3.
User’s Manual 4.3.6.4.2 Parallel Port IRQ This option is only valid if the Onboard Parallel Port option is not set to Disabled. This option sets the IRQ used by the parallel port. 4.3.6.4.3 Parallel Port DMA Channel This option is only available if On Board Parallel Port is set to fixed I/O address and the setting of Parallel Port Mode is ECP. This option sets the DMA channel used by ECPcapable parallel port. 4.3.6.
ECB-865 4.3.7 Hardware Monitor Setup Defaults This setup describes current CPU surface temperature status detected from hardware monitor sensor. The status showed on screen will include: 4.3.7.
User’s Manual 4.3.7.2 CPU Temperature 4.3.7.3 System Temperature 4.3.7.4 Power Fan 4.3.7.5 System Fan 4.3.7.6 +Vbbat 4.3.7.7 +5VSB 4.3.7.8 +5.000V 4.3.7.9 +12.000V 4.3.7.10 -12.000V 4.3.7.11 -5.000V 4.4 Flash BIOS Utility Utilize AMI Flash BIOS programming utility to update on-board BIOS for the future new BIOS version. Please contact your technical window to get this utility if necessary. Note: Remark or delete any installed Memory Management Utility (such as HIMEM.SYS, EMM386.
ECB-865 5. Driver Installation 5.1 5.1.1 Driver Installation for Ethernet Adapter Windows 9x The best way to install the driver for the Ethernet controller is to use the plug and play system of Windows 9x. The following procedures illustrate how the installation can be done. 1. If a driver for the Ethernet controller is already installed, it must be removed first. This can be done by following the steps shown below.
User’s Manual • If the ‘Network adapters’ line is present, expand the line and remove the PCI Ethernet Adapter. This is done by selecting the line and clicking the ‘Remove’ button. Before removal of the adapter(s), your screen might look like this: • When all adapters are removed (or none were present), a new driver can be installed now. 2. Reboot the computer. 3. During the boot up the network adapter should be detected as shown below. Click the ‘Next’ button.
ECB-865 4. Click the ‘Next’ button to continue the driver installation. 5. Specify the location of network adapter and click ‘Next’ (see below).
User’s Manual 6. Click the ‘Next’ button to install the network adapter driver. 7. Click the ‘Next’ button.
ECB-865 8. Click the ‘Finish’ button. 9. To complete the installation, reboot the computer by clicking the ‘Yes’ button in the window shown below. 10.After the system restarts, the network adapter should be installed. Protocols, clients etc. may now be installed for the network in use. Further configuration of the adapter may be made in the ‘Advanced’ section of the driver properties.
User’s Manual 5.1.2 Windows NT 4.0 Ethernet Installation A driver for the Intel 82559 Ethernet controller on board is included in the attached supporting CD-ROM. The driver for this adapter is denoted ‘Intel® PRO Adapter’. This driver may be installed in two ways: • During the installation process where the network may be configured as an integrated part. In this case the adapter may be chosen or auto-detected when the network adapter is to be installed. • In the network settings after Windows NT 4.
ECB-865 2. Double click the ‘Network’ icon and click the ‘Adapters’ tab on the following window. A window as the one shown below should now appear. 3. Click the ‘Add...’ button, and the following window should appear.
User’s Manual 4. Click the ‘Have Disk…’ button to install the Network adapter driver from CD-ROM. A window as the one shown below should now appear. 5. Locate the path of Network adapter driver and click the ‘OK’ button.
ECB-865 6. Select the ‘Intel® PRO Adapter’ from the list (as shown below) and click the ‘OK’ button. The Network adapter driver should now be installed. 7. After the driver installation is complete, Protocols, Services etc. may now be configured for the network to be used. An example is shown below.
User’s Manual 8. Click ‘Close’ to accept the settings. 9. IP Address, DNS etc. may now be configured for the network to be used. Click ‘OK’ to accept the settings. 10.To complete the driver installation, reboot the computer by clicking the ‘Yes’ button in the window shown below.
ECB-865 5.2 5.2.1 Driver Installation for Display Adapter Windows 9x The following steps will install the display driver for the ‘Chips & Technologies 69000 PCI’ display controller. 1. Click the ‘Start’ button on the task bar, select ‘Settings’ and ‘Control Panel’ from the sub-menu. This should start the Control Panel as shown below: 2. Double click the ‘Display’ icon and select the ‘Settings’ tab as shown below.
User’s Manual 3. Click the ‘Advanced…’ button. This will show the following window. Click the ‘Change…’ button in the Adapter Type frame to select another driver. Your display will probably have another driver then the ‘Standard PCI Graphics Adapter (VGA)’ installed at this moment. 4. Click the ‘Next’ to update the display driver.
ECB-865 5. Click the ‘Next’ to continue the display driver installation. 6. Locate the path of Graphics adapter driver and click the ‘Next’ button.
User’s Manual 7. The driver files will now be read and the display adapter is shown as the following. Click the ‘Next’ button to install the display driver. 8. Click the ‘Finish’ button. 9. To complete the display driver installation, reboot the computer by clicking the ‘Yes’ button in the window shown below.
ECB-865 10.Further configuration of the display adapter may be made from the ‘Display Properties’ window (follow step 1 above). The ‘Settings’ tab allows you to change resolution, number of colours etc. as shown below.
User’s Manual 5.2.2 Windows NT 4.0 Display Installation A display driver for Windows NT 4.0 is supplied with the system on the Supporting CDROM. The driver installation may be performed by following steps shown below: 1. Start the control panel by clicking the ‘Start’ button, click ‘Settings’ and ‘Control Panel’ from the sub-menu. Double click the ‘Display’ icon in the control panel as shown below. 2. On the Display properties window, click the ‘Settings’ tab as shown below.
ECB-865 3. Click the ‘Display Type…’ button and the following window should appear. Click the ‘Change…’ button to select another driver. 4. Click the ‘Have Disk…’ button. 5. The directory for the drivers may now be entered. Type A\:WINNT40 as shown below. Insert the ‘Display driver disk’ and click ‘OK’.
User’s Manual 6. The display driver should now be listed as shown below. Click ‘OK’ to accept. 7. Since this driver is not part of the NT4.0 package, the following message will be shown. 8. To proceed the driver installation, click the ‘Yes’ button. The driver will now be installed, and the following message should be shown shortly. 9. Click ‘OK’ and close the ‘Display Type’ and ‘Display Properties’ windows by clicking the ‘Close’ button in each window. 10.
ECB-865 11.After the reboot, display resolution etc. may be configured in the ‘Display Properties’ window (opened by following steps 1 and 2 above). An example is shown below. 12.Before accepting the new settings by pressing ‘OK’, a test should be performed by clicking the ‘Test’ button.
User’s Manual 6.
ECB-865 Appendix A: BIOS Revisions BIOS Rev.
User’s Manual Appendix B: System Resources Memory Map The following table indicates memory map of ECB-865. The address ranges specify the runtime code length.
ECB-865 I/O – Map Certain I/O addresses are subject to change during boot as PnP managers may relocate devices or functions. The addresses shown in the table are typical locations.
User’s Manual I/O Port Description 03C0h-03DFh Intel(R) 82815 Graphics Controller 03F0h-03F3h Standard Floppy Disk Controller 03F4h-03F5h Standard Floppy Disk Controller 03F6h-03F6h Primary Ultra ATA Controller 03F8h-03FFh Communications Port (COM1) 0400h-047Fh Motherboard resources 0440h-044Fh Motherboard resources 04D0h-04D1h Motherboard resources 0CF8h-0CFFh PCI bus C000h-CFFFh Intel(R) 82801BA PCI Bridge - 244E CE80h-CEBFh Intel(R) PRO/100 VE Network Connection CF00h-CF3Fh Inte
ECB-865 Interrupt Usage. The onboard Intel 82801BA provides an ISA compatible interrupt controller with functionality as two 8259A interrupt controllers. The two controllers are cascaded to provide 13 external interrupts. The actual interrupt settings depend on the PnP handler, the table below indicates the typical settings.
User’s Manual DMA-channel Usage The DMA circuitry incorporates the functionality of two 8237 DMA controllers with seven programmable channels. The controllers are referenced DMA Controller 1 for channels 03 and DMA Controller 2 for channels 4-7. Channel 4 is by default used to cascade the two controllers.
ECB-865 Appendix C: AMIBIOS Power-On Self Test Every time the system is powered on, AMIBIOS executes a power-on self test. In case of errors they are reported in one of two ways. If the error occurs before the display device is initialised, a series of beeps sound. Beep codes indicate that a fatal error has occurred. AMIBIOS Beep Codes are described in the table below. If it beeps… 1, 2, or 3 times Then… Re-insert the memory SIMMs. If the system still beeps replace the memory.
User’s Manual APPENDIX D: AMIBIOS POST Check Point List AMIBIOS provides all IBM standard Power On Self Test (POST) routines as well as enhanced AMIBIOS POST routines. The POST routines support CPU internal diagnostics. The POST checkpoint codes are accessible via the Manufacturing Test Port (I/O port 80h). Whenever a recoverable error occurs during the POST, the system BIOS will display an error message describing the message and explaining the problem in detail so that the problem can be corrected.
ECB-865 Bootblock Recovery Codes — The bootblock recovery checkpoint hex codes are listed in order of execution: Code Description E0 The onboard floppy controller if available is initialized. Next, beginning the base 512KB memory test. E1 Initializing the interrupt vector table next. E2 Initializing the DMA and Interrupt controllers next. E6 Enabling the floppy drive controller and Timer IRQs. Enabling internal cache memory. ED EE Initializing the floppy drive.
User’s Manual Uncompressed Initialization Codes — The following runtime checkpoint hex codes are listed in order of execution. These codes are uncompressed in F0000h shadow RAM. Code 03 Description The NMI is disabled. Next, checking for a soft reset or a power on condition. 05 The BIOS stack has been built. Next, disabling cache memory. 06 Uncompressing the POST code next. 07 Next, initializing the CPU and the CPU data area. 08 The CMOS checksum calculation is done next.
ECB-865 Code 2A Description Bus initialization system, static, output devices will be done next, if present. 2B Passing control to the video ROM to perform any required configuration before the video ROM test. 2C To look for optional video ROM and give control. 2D The video ROM has returned control to BIOS POST. Performing any required processing after the video ROM had control. 2E Completed podt-video ROM test processing.
User’s Manual Code 4B Description The amount of memory above 1MB has been found and verified. Checking for a soft reset and clearing the memory below 1MB for the soft reset next. If this is a power on situation, going to checkpoint 4Eh next. 4C The memory below 1MB has been cleared via a soft reset. Clearing the memory above 1MB next. 4D The memory above 1MB has been cleared via soft reset. Saving the memory size next. Going to checkpoint 52h next.
ECB-865 Code 81 Description A keyboard reset error or stuck key was found. Issuing the keyboard Controller interface test command next. 82 The keyboard controller interface test completed. Writing the command byte and initializing the circular buffer next. 83 Command byte written, Global data init done. To check for lock-key. 84 Locked key checking is over. Checking for a memory size mismatch with CMOS RAM data next. 85 The memory size check is done.
User’s Manual Code 9A Description Return after setting timer and printer base address. Going to set the RS-232 base address. 9B Returned after setting the RS-232 base address. Performing any required Initialization before the Coprocessor test next. 9C Required initialization before the Coprocessor test is over. Initializing the Coprocessor next. 9D Coprocessor initialized. Going to do any initialization after Coprocessor test. 9E Initialization after the Coprocessor test is complete.
