Information

Power Management and Efciency Features
Features Benefits
IEEE 802.3az - Energy Efficient Ethernet (EEE) • Power consumption by the PHY is reduced by approximately 50%; link transitions to low power Idle (LPI)
state as defined in the IEEE 802.3az (EEE) standard
DMA Coalescing • Reduces platform power consumption by coalescing, aligning, and synchronizing DMA
• Enables synchronizing port activity and power management of memory, CPU and RC internal circuitry
Smart Power Down (SPD) at S0 no link/Sx no link • PHY powers down circuits and clocks that are not required for detection of link activity
Active State Power Management (ASPM) • Optionality Compliance bit enables ASPM or runs ASPM compliance tests to support entry to L0s
LAN disable function • Option to disable the LAN Port and/or PCIe Function. Disabling just the PCIe function but keeping the
LAN port that resides on it fully active (for manageability purposes and BMC pass-through traffic).
Full wake up support::
• Advanced Power Management (APM) Support–
[formerly Wake on LAN]
• Advanced Configuration and Power Interface
(ACPI) specification v2.0c
• Magic Packet* wake-up enable with unique MAC
address
• APM - Designed to receive a broadcast or unicast packet with an explicit data pattern (Magic Packet) and
assert a signal to wake up the system
• ACPI - PCIe power management based wake-up that can generate system wake-up events from a num-
ber of sources
ACPI register set and power down functionality sup-
porting D0 and D3 states
• A power-managed link speed control lowers link speed (and power) when highest link performance is not
requireds
MAC Power Management controls • Power management controls in the MAC /PHY enable the device to enter a low-power state
Low Power Link Up - Link Speed Control • Enables a link to come up at the lowest possible speed in cases where power is more important than
performance
Power Management Protocol Offload (Proxying) • Avoid spurious wake up events and reduce system power consumption when the device is in D3 low
power state and system in in S3 or S4 low power states
Stateless Ofoads and Performance Features
Features Benefits
TCP/UDP, IPv4 checksum offloads (Rx/ Tx/Large-
send); Extended Tx descriptors)
• More offload capabilities and improved CPU usage
• Checksum and segmentation capability extended to new standard packet type
IPv6 support for IP/TCP and IP/UDP receive check-
sum offload
• Improved CPU usage
Transmit Segmentation Offloading (TSO) (IPv4, IPv6) • Increased throughput and lower processor usage
Interrupt throttling control • Limits maximum interrupt rate and improves CPU usage
Legacy and Message Signal Interrupt (MSI) • Interrupt mapping.
Message Signal Interrupt Extension (MSI-X) • Dynamic allocation of up to 5 vectors per port
Intelligent interrupt generation • Enhanced software device driver performance
Receive Side Scaling (RSS) for Windows* • Up to four queues per port
Scalable I/O for Linux environments (IPv4, IPv6, TCP/
UDP)
• Improves the system performance related to handling of network data on multiprocessor systems
Support for packets up to 9.5 KB ( Jumbo Frames) • Enables faster and more accurate throughput of data
Low Latency Interrupts • Based on the sensitivity of the incoming data, the controller can bypass the automatic moderation of
time intervals between the interrupts
Header/packet data split in receive • Helps the driver to focus on the relevant part of the packet without the need to parse it
PCIe v2.1 TLP Processing Hint Requester • Provides hints on a per transaction basis to facilitate optimized processing of
Descriptor ring management hardware for Transmit
and Receive
• Optimized descriptor fetch and write-back for efficient system memory and PCIe bandwidth usage
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