Data Sheet

Interconnects—Ethernet Controller I210

In the case of a collision, the PHY/SGMII detects the collision and asserts the COL signal to the MAC.

Frame transmission stops within four link clock times and then the I210 sends a JAM sequence onto the

link. After the end of a collided transmission, the I210 backs off and attempts to re-transmit per the

standard CSMA/CD method.

Note: The re-transmissions are done from the data stored internally in the I210 MAC transmit

packet buffer (no re-access to the data in host memory is performed).

The MAC behavior is different if a regular collision or a late collision is detected. If a regular collision is

detected, the MAC always tries to re-transmit until the number of excessive collisions is reached. In

case of late collision, the MAC retransmission is configurable. In addition, statistics are gathered on late

collisions.

In the case of a successful transmission, the I210 is ready to transmit any other frame(s) queued in the

MAC's transmit FIFO, after the minimum inter-frame spacing (IFS) of the link has elapsed.

During transmit, the PHY is expected to signal a carrier-sense (assert the CRS signal) back to the MAC

before one slot time has elapsed. The transmission completes successfully even if the PHY fails to

indicate CRS within the slot time window. If this situation occurs, the PHY can either be configured

incorrectly or be in a link down situation. Such an event is counted in the transmit without CRS statistic

When operating in half duplex mode, the elasticity FIFO in the PHY should be programmed to its

minimum size by setting the Copper Transmit FIFO Depth field to 00b (depth of 16 bits). See

Section 8.27.3.23).

3.7.3 SerDes/1000BASE-BX, SGMII and 1000BASE-KX Support

The I210 can be configured to follow either SGMII, SerDes/1000BASE-BX or 1000BASE-KX standards.

When in SGMII mode, the I210 can be configured to operate in 1 Gb/s, 100 Mb/s or 10 Mb/s speeds.

When in the 10/100 Mb/s speed, the I210 can be configured to half-duplex mode of operation. When

configured for SerDes/1000BASE-BX or 1000BASE-KX operation, the port supports only 1 Gb/s, full-

duplex operation. Since the serial interfaces are defined as differential signals, internally the hardware

has analog and digital blocks. Following is the initialization/configuration sequence for the analog and

digital blocks.

3.7.3.1 SerDes/1000BASE-BX, SGMII and 1000BASE-KX Analog Block

The analog block might require some changes to its configuration registers in order to work properly.

There is no special requirement for designers to do these changes as the hardware internally updates

the configuration using a default sequence or a sequence loaded from the Flash.

3.7.3.2 SerDes/1000BASE-BX, SGMII and 1000BASE-KX PCS Block

The link setup for SerDes/1000BASE-BX, 1000BASE-KX and SGMII are described in sections 3.7.4.1,

3.7.4.2 and 3.7.4.3 respectively.

3.7.3.3 GbE Physical Coding Sub-Layer (PCS)

The I210 integrates the 802.3z PCS function on-chip. The on-chip PCS circuitry is used when the link

interface is configured for SerDes/1000BASE-BX, 1000BASE-KX or SGMII operation and is bypassed for

internal PHY mode.