Data Sheet

Ethernet Controller I210 —Interconnects

— Opcode = 01b (write).

— REGADD = Register address of the specific register to be accessed (0 through 31).

— Data = Specific data for desired control of the PHY.

3. The MAC applies the following sequence on the MDIO signal to the PHY:

4. The I210 asserts an interrupt indicating MDIO Done if the Interrupt Enable bit was set.

5. The I210 sets the Ready bit in the MDIC register to indicate that the write operation completed.

6. The CPU might issue a new MDIO command.

Note: A MDIO read or write might take as long as 64 s from the processor write to the Ready bit

assertion.

If an invalid opcode is written by software, the MAC does not execute any accesses to the PHY

registers.

If the PHY does not generate a 0b as the second bit of the turn-around cycle for reads, the MAC aborts

the access, sets the E (error) bit, writes 0xFFFF to the data field to indicate an error condition, and sets

the Ready bit.

Note: After a PHY reset, access through the MDIC register should not be attempted for 300 s.

3.7.2.3 Duplex Operation with Copper PHY

The I210 supports half-duplex and full-duplex 10/100 Mb/s MII mode either through an internal copper

PHY or SGMII interface. However, only full-duplex mode is supported when SerDes/1000BASE-BX or

1000BASE-KX modes are used or in any 1000 Mb/s connection.

Configuring the I210 duplex operation can either be forced or determined via the auto-negotiation

process. Refer to Section 3.7.4.4 for details on link configuration setup and resolution.

3.7.2.3.1 Full Duplex

All aspects of the IEEE 802.3, 802.3u, 802.3z, and 802.3ab specifications are supported in full-duplex

operation. Full-duplex operation is enabled by several mechanisms, depending on the speed

configuration of the I210 and the specific capabilities of the link partner used in the application. During

full-duplex operation, the I210 can transmit and receive packets simultaneously across the link

interface.

In full-duplex, transmission and reception are delineated independently by the GMII/MII control

signals. Transmission starts TX_EN is asserted, which indicates there is valid data on the TX_DATA bus

driven from the MAC to the PHY/PCS. Reception is signaled by the PHY/PCS by the asserting the RX_DV

signal, which indicates valid receive data on the RX_DATA lines to the MAC.

3.7.2.3.2 Half Duplex

In half-duplex operation, the MAC attempts to avoid contention with other traffic on the link by

monitoring the CRS signal provided by the PHY and deferring to passing traffic. When the CRS signal is

de-asserted or after a sufficient Inter-Packet Gap (IPG) has elapsed after a transmission, frame

transmission begins. The MAC signals the PHY/PCS with TX_EN at the start of transmission.