Data Sheet

Interconnects—Ethernet Controller I210

The external port PHY address is written in the MDICNFG.PHYADD register field, which is loaded from

the Initialization Control 4 Flash word following reset.

Note: When the dedicated SFPx_I2C pins are not used for I

C, an alternative I

C interface bus can

be run over SDP 0 and SDP2 pins, using the I2CCMD register set (refer to Section 3.5.2).

3.7.2.2.1 Detecting an External I

C or MDIO Connection

When the CTRL_EXT.I2C Enabled bit is set to 1b, software can recognize type of external PHY control

bus (MDIO or I

C) connection according to the values loaded from the Flash to the

MDICNFG.Destination bit and the CTRL_EXT.LINK_MODE field in the following manner:

•External I

C operating mode - MDICNFG.Destination equals 0b and CTRL_EXT.LINK_MODE is not

equal to 0b.

• External MDIO Operating mode - MDICNFG.Destination equals 1b and CTRL_EXT.LINK_MODE is not

equal to 0b.

3.7.2.2.2 MDIC and MDICNFG Register Usage

For a MDIO read cycle, the sequence of events is as follows:

1. If default MDICNFG register values loaded from Flash need to be updated. The processor performs

a PCIe write access to the MDICNFG register to define the:

— PHYADD = Address of external PHY.

— Destination = Internal or external PHY.

2. The processor performs a PCIe write cycle to the MDIC register with:

— Ready = 0b

— Interrupt Enable set to 1b or 0b

— Opcode = 10b (read)

— REGADD = Register address of the specific register to be accessed (0 through 31).

3. The MAC applies the following sequence on the MDIO signal to the PHY:

<PREAMBLE><01><10><PHYADD><REGADD><Z> where Z stands for the MAC tri-stating the

MDIO signal.

4. The PHY returns the following sequence on the MDIO signal<0><DATA><IDLE>.

5. The MAC discards the leading bit and places the following 16 data bits in the MII register.

6. The I210 asserts an interrupt indicating MDIO Done if the Interrupt Enable bit was set.

7. The I210 sets the Ready bit in the MDIC register indicating the read completed.

8. The processor might read the data from the MDIC register and issue a new MDIO command.

For a MDIO write cycle, the sequence of events is as follows:

1. If default MDICNFG register values loaded from Flash need to be updated. The processor performs

a PCIe write cycle to the MDICNFG register to define the:

— PHYADD = Address of external PHY.

— Destination = Internal or external PHY.

2. The processor performs a PCIe write cycle to the MDIC register with:

— Ready = 0b.

— Interrupt Enable set to 1b or 0b.