Data Sheet

Ethernet Controller I210 —Interconnects
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The internal copper PHY supports 10/100/1000BASE-T signaling and is capable of performing intelligent
power-management based on both the system power-state and LAN energy-detection (detection of
unplugged cables). Power management includes the ability to shut-down to an extremely low
(powered-down) state when not needed, as well as the ability to auto-negotiate to lower-speed 10/100
Mb/s operation when the system is in low power-states.
3.7.2 MAC Functionality
3.7.2.1 Internal GMII/MII Interface
The I210’s MAC and PHY/PCS communicate through an internal GMII/MII interface that can be
configured for either 1000 Mb/s operation (GMII) or 10/100 Mb/s (MII) mode of operation. For proper
network operation, both the MAC and PHY must be properly configured (either explicitly via software or
via hardware auto-negotiation) to identical speed and duplex settings.
All MAC configuration is performed using Device Control registers mapped into system memory or I/O
space; an internal MDIO/MDC interface, accessible via software, is used to configure the internal PHY.
In addition an external MDIO/MDC interface is available to configure external PHY’s that are connected
to the I210 via the SGMII interface.
3.7.2.2 MDIO/MDC PHY Management Interface
The I210 implements an IEEE 802.3 MII Management Interface, also known as the Management Data
Input/Output (MDIO) or MDIO interface, between the MAC and a PHY. This interface provides the MAC
and software the ability to monitor and control the state of the PHY. The MDIO interface defines a
physical connection, a special protocol that runs across the connection, and an internal set of
addressable registers. The interface consists of a data line (MDIO) and clock line (MDC), which are
accessible by software via the MAC register space.
• Management Data Clock (MDC): This signal is used by the PHY as a clock timing reference for
information transfer on the MDIO signal. The MDC is not required to be a continuous signal and can
be frozen when no management data is transferred. The MDC signal has a maximum operating
frequency of 2.5 MHz.
• MDIO: This bi-directional signal between the MAC and PHY is used to transfer control and status
information to and from the PHY (to read and write the PHY management registers).
Software can use MDIO accesses to read or write registers of the internal PHY, internal SerDes, or an
external SGMII PHY, by accessing the I210's MDIC register (refer to Section 8.2.4). MDIO configuration
setup (internal/ External PHY, PHY Address and Shared MDIO) is defined in the MDICNFG register (refer
to Section 8.2.5). By selecting Page 26 via PHYREG 22 register, internal SerDes registers can be
accessed.
When working in SGMII/SerDes mode, the external PHY (if it exists) can be accessed either through
MDC/MDIO as previously described, or via a two wire I
2
C interface bus using the I2CCMD register (refer
to Section 8.17.8). The two wire I
2
C interface bus or the MDC/MDIO bus are connected via the same
pins, and thus are mutually exclusive. In order to be able to control an external device, either by I
2
C or
MDC/MDIO, the 2-wires SFP Enable bit in Initialization Control 3 Flash word, that’s loaded into the
CTRL_EXT.I2C Enabled register bit, should be set.
As the MDC/MDIO command can be targeted either to the internal PHY or to an external bus, the
MDICNFG.destination bit is used to define the target of the transaction. Following reset, the value of the
MDICNFG.destination bit is loaded from the External MDIO bit in the Initialization Control 3 Flash word.
When the MDICNFG.destination is clear, the MDIO access is always to the internal PHY and the PHY
address is ignored.