Data Sheet

Ethernet Controller I210 —Interconnects

Once the host driver is up and it determines that hardware is functional, it might reset the watchdog

timer to indicate that the I210 is functional. The software device driver should then re-arm the timer

periodically. If the timer is not re-armed after pre-programmed timeout, an interrupt is sent to

firmware and a pre-programmed SDP0 pin is asserted. Additionally the ICR.Software WD bit can be set

to give an interrupt to the software device driver when the timeout is reached.

The SDP0 pin on which the watchdog timeout is indicated, is defined via the CTRL.SDP0_WDE bit. In

this mode, the CTRL.SDP0_IODIR should be set to output. The CTRL.SDP0_DATA bit indicates the

polarity of the indication. Setting the CTRL.SDP0_WDE bit causes the watchdog timeout indication to be

routed to this SDP0 pin.

The register controlling the watchdog timeout feature is the WDSTP register. This register enables

defining a time-out period and the activation of this mode. Default watchdog timeout activation and

timeout period can be set in the Flash.

The timer is re-armed by setting the WDSWSTS.Dev_functional bit.

If software needs to trigger the watchdog immediately because it suspects hardware is stuck, it can set

the WDSWSTS.Force_WD bit. It can also supply firmware the cause for the watchdog, by placing

additional information in the WDSWSTS.Stuck Reason field.

Note: The watchdog circuitry has no logic to detect if hardware is not functional. If the hardware is

not functional, the watchdog might expire due to software not being able to access the

hardware, thus indicating there is potential hardware problem.

3.5.3.1 Watchdog Re-arm

After a watchdog indication was received, in order to re-arm the mechanism the following flow should

be used:

1. Clear WD_enable bit in the WDSTP register.

2. Clear SDP0_WDE bit in CTRL register.

3. Set SDP0_WDE bit in CTRL register.

4. Set WD_enable bit in the WDSTP register.

3.5.4 LEDs

The I210 provides three LEDs on the port that can be used to indicate different statuses of the traffic.

The default setup of the LEDs is done via Flash word offsets 0x1C and 0x1F. This setup is reflected in

the LEDCTL register. Each software device driver can change its setup individually. For each of the

LEDs, the following parameters can be defined:

• Mode: Defines which information is reflected by this LED. The encoding is described in the LEDCTL

• Polarity: Defines the polarity of the LED.

• Blink mode: Determines whether or not the LED should blink or be stable.

In addition, the blink rate of all LEDs can be defined. The possible rates are 200 ms or 83 ms for each

phase. There is one rate for all the LEDs.