Data Sheet

Interconnects—Ethernet Controller I210

However, if the system powers up in S3 state or if a firmware reset event occurs while the

system was in S3, no proxy offload is performed until the system resumes S0 and the proxy

code is re-loaded into the device.

After PHY reset events, ROM-firmware (as well as RAM-firmware) is responsible to parse the PHY

accesses accordingly.

3.5 Configurable I/O Pins

3.5.1 General-Purpose I/O (Software-Definable Pins)

The I210 has four software-defined pins (SDP pins) that can be used for miscellaneous hardware or

software-controllable purposes. These pins can each be individually configurable to act as either input

or output pins. The default direction of each of the four pins is configurable via the Flash as well as the

default value of any pins configured as outputs. To avoid signal contention, all four pins are set as input

pins until after the Flash configuration has been loaded.

In addition to all four pins being individually configurable as inputs or outputs, they can be configured

for use as General-Purpose Interrupt (GPI) inputs. To act as GPI pins, the desired pins must be

configured as inputs. A separate GPI interrupt-detection enable is then used to enable rising-edge

detection of the input pin (rising-edge detection occurs by comparing values sampled at the internal

clock rate as opposed to an edge-detection circuit). When detected, a corresponding GPI interrupt is

indicated in the Interrupt Cause register.

The use, direction, and values of SDP pins are controlled and accessed using fields in the Device Control

(CTRL) register and Extended Device Control (CTRL_EXT) register.

The SDPs can be used for special purpose mechanisms such as a watchdog indication (refer to

Section 3.5.3), IEEE 1588 support (refer to Section 7.8) or an I

C interface bus (refer to

Section 3.5.2).

3.5.2 I

C Over SDP

The I

C usage of SDP pins must be enabled by setting the I2C_ON_SDP_EN bit to 1b in Flash word

0x20. This relates to the SDP 0 and SDP 2 pins, which operate as I2C_CLK and I2C_DATA, respectively.

The I

C interface operates via the I2CCMD and I2CPARAMS register set (refer to Section 8.17.8). Since

this register set can be used by either software or firmware in alternation, its ownership must be

acquired/released via the semaphore ownership taking/release flows described in Section 4.6.

Note: I

C over SDP pins mode is mutually exclusive with running I

C over the SFPx_I2C pins.

3.5.3 Software Watchdog

In some situations it might be useful to give an indication to manageability firmware or to external

devices that the I210 hardware or the software device driver is not functional. For example, in a pass-

through NIC, the I210 might be bypassed if it is not functional. In order to provide this functionality, a

watchdog mechanism is used. This mechanism can be enabled by default, according to Flash

configuration.