Data Sheet

Diagnostics—Ethernet Controller I210
849
14.0 Diagnostics
14.1 Customer Visible Features
14.1.1 JTAG Test Mode Description
The I210 includes a JTAG (TAP) port that is compliant with the IEEE standard 1149.1, 2001 Edition
(JTAG). Institute of Electrical and Electronics Engineers (IEEE).
The TAP controller is accessed serially through the four dedicated pins TCK, TMS, TDI, and TDO. TMS,
TDI, and TDO operate synchronously with TCK which is independent of all other clock within the I210.
This interface can be used for test and debug purposes. System board interconnects can be DC tested
using the boundary scan logic in pads. Table 14-1 shows TAP controller related pin descriptions.
Table 14-2 describes the TAP instructions supported by the I210. The default instruction after JTAG
reset is IDCODE.
Table 14-1. TAP Controller Pins
Signal I/O Description
TCK In
Test clock input for the test logic defined by IEEE1149.1.
Note: Signal should be connected to ground through a 3.3 K
 pull-down resistor.
TDI In
Test Data Input. Serial test instructions and data are received by the test logic at this pin.
Note: Signal should be connected to VCC33 through a 3.3 K
 pull-up resistor.
TDO O/D
Test Data Output. The serial output for the test instructions and data from the test logic defined in IEEE1149.1.
Note: Signal should be connected to VCC33 through a 3.3 K
 pull-up resistor.
TMS In
Test Mode Select input. The signal received at TMS is decoded by the
TAP controller to control test operations.
Note: Signal should be connected to VCC33 through a 3.3 K
 pull-up resistor.