Data Sheet

Ethernet Controller I210 —Interconnects

Note: Software uses the autoload bus write mechanism because writing into registers is not always

possible to set internal hardware structures.

3.4.6 I210 Init Flow

Once the init flow detects no Flash device is present, a POR or a firmware reset event, the ROM-based

firmware code jumps to this flow from step 2 of the flow described in Section 3.3.11.2.

1. If this is the first time this flow is entered after POR, then ROM-firmware parses the iNVM structure

to handle PHY register auto-load structures (if there are such in iNVM).

2. ROM-firmware parses the iNVM structure to detect the presence of a word auto-load structure for

iNVM word 0x0A:

a. If the structure is found and HI_DISABLE bit is set to 1b, then exit this flow.

3. ROM-firmware sets the HICR.Memory Base Enable bit to 1b, and HICR.Enable to 1b. This has the

effect of enabling the host interface.

4. ROM-firmware sets FWSM.FW_Mode field to 100b (host interface only), the FWSM.FW_Val_Bit to

1b, and issues an ICR.MNG interrupt to the host for notifying it that the device is ready for the

proxy code load.

5. ROM-firmware polls the HICR.C bit until it is set to 1b by the host. This is the indication used by the

host to notify firmware that the proxy code was loaded.

6. When the software device driver is up, it detects it is a the I211 SKU (device ID read as 0x1539)

and it waits until FWSM.FW_Mode is read as 100b (host interface only) and the FWSM.FW_Val_Bit

is read as 1b.

7. The software device driver resets the port by setting CTRL.RST and waits for EEC.AUTO_RD to be

read as 1b.

8. The software device driver resets the firmware by setting HICR.FWRE to 1b first, and then by

setting HICR.FWR to 1b, which has the effect of re-entering the ROM-firmware into step 1.

9. Each time the system exits from a sleep state, or once the software device driver gets the interrupt

issued by firmware at step 2, the software device driver checks whether the FWSM.FW_Mode is

read as 100b (host interface only) and the FWSM.FW_Val_Bit is read as 1b. This is the method used

by firmware to request re-load of the proxy code.

10. If a proxy code has to be loaded, then the software device driver sets its current internal RAM base

address to 0x10000. Otherwise, the software device driver exits the flow.

11. The software device driver copies its current internal RAM base address into the HIBBA register.

12. The software device driver writes consecutive locations from address 0x8800 up to 0x8BFF with the

next 1 KB of the proxy code, in Dwords (32-bit) chunks ordered in little endian.

13. The software device driver increments its current internal RAM base address by 1 KB.

14. The software device driver repeats steps 10 to 12 until the entire proxy code is written (or until the

50 KB limit is reached).

15. The software device driver sets the HICR.C bit to notify the ROM-firmware that the proxy code load

completed.

16. ROM-firmware starts the proxy code execution from internal RAM address 0x10000.

17. Once RAM-firmware completes it’s init sequence and is ready to receive commands from host, it

sets FWSM.FW_Mode to 001b (the I211 mode) and the FW_Val_Bit to 1b, and it clears the HICR.C

bit to notify the host that the host interface is ready to receive commands.

Note: Once loaded, the firmware runs the proxy code even when the system is in a sleep state. It is

the software device driver’s responsibility to reset the firmware prior to entering Sx.