Data Sheet

Ethernet Controller I210 —Design Considerations
840
12.11 XOR Testing
A common board or system-level manufacturing test for proper electrical continuity between the I210
and the board is some type of cascaded-XOR or NAND tree test. The I210 implements an XOR tree
spanning most I/O signals. The component XOR tree consists of a series of cascaded XOR logic gates,
each stage feeding in the electrical value from a unique pin. The output of the final stage of the tree is
visible on an output pin from the component.
Figure 12-28.XOR Tree Concept
By connecting to a set of test-points or bed-of-nails fixture, a manufacturing test fixture can test
connectivity to each of the component pins included in the tree by sequentially testing each pin, testing
each pin when driven both high and low, and observing the output of the tree for the expected signal
value and/or change.
Note: Some of the pins that are inputs for the XOR test are listed as “may be left disconnected” in
the pin descriptions. If XOR test is used, all inputs to the XOR tree must be connected.
When the XOR tree test is selected, the following behaviors occur:
• Output drivers for the pins listed as “tested” are all placed in high-impedance (tri-state) state to
ensure that board/system test fixture can drive the tested inputs without contention.
• Internal pull-up and pull-down devices for pins listed as “tested” are also disabled to further ensure
no contention with the board/system test fixture.
• The XOR tree is output on the LED1 pin.
To enter the XOR tree mode, a specific JTAG pattern must be sent to the test interface. This pattern is
described by the following TDF pattern: (dh = Drive High, dl = Drive Low)
dh (JTAG_TDI) dl(JTAG_TCK,JTAG_TMS);
dh(JTAG_TCK);
dl(JTAG_TCK);
dh(JTAG_TMS);
loop 2
dh(JTAG_TCK);
dl(JTAG_TCK);
end loop
dl(JTAG_TMS);
loop 2
dh(JTAG_TCK);
dl(JTAG_TCK);
end loop