Data Sheet

Ethernet Controller I210 —Design Considerations
836
12.7.3 Power and Ground Planes
Good grounding requires minimizing inductance levels in the interconnections and keeping ground
returns short, signal loop areas small, and power inputs bypassed to signal return, will significantly
reduce EMI radiation.
The following guidelines help reduce circuit inductance in both backplanes and motherboards:
• Route traces over a continuous plane with no interruptions. Do not route over a split power or
ground plane. If there are vacant areas on a ground or power plane, avoid routing signals over the
vacant area. This increases inductance and EMI radiation levels.
• Separate noisy digital grounds from analog grounds to reduce coupling. Noisy digital grounds may
affect sensitive DC subsystems.
• All ground vias should be connected to every ground plane; and every power via should be
connected to all power planes at equal potential. This helps reduce circuit inductance.
• Physically locate grounds between a signal path and its return. This minimizes the loop area.
• Avoid fast rise/fall times as much as possible. Signals with fast rise and fall times contain many
high frequency harmonics, which can radiate EMI.
• The ground plane beneath a magnetics module should be split. The RJ45 connector side of the
transformer module should have chassis ground beneath it.
• Power delivery traces should be a minimum of 20 mils wide at all places from the source to the
destination with neck down at package pins. The distribution of power is better done with a copper
plane or shape under the PHY. This provides low inductance connectivity to decoupling capacitors.
Decoupling capacitors should be placed as close as possible to the point of use and should avoid
sharing vias with other decoupling capacitors. Decoupling capacitor placement control should be
done for the PHY as well as any external regulators if used.
• An SVR fly capacitor should be preferentially placed near pin 37 and 40 with wide traces to limit in-
line inductance.
• SVR output routing: AVDD09_VR_O (pin 38) should be connected with wide traces and plane shape
using more than one via for a layer change to VDD09 pins. The net should have recommended bulk
and decoupling capacitance strongly joined into this route. AVDD15_VR_O (pin 39) has similar
requirements but has lower currents so it might require only wide traces and a single via for any
layer change.
12.8 Device Disable
For a LOM design, it might be desirable for the system to provide BIOS-setup capability for selectively
enabling or disabling LOM devices. This enables designers more control over system resource-
management, avoid conflicts with add-in NIC solutions, etc. The I210 provides support for selectively
enabling or disabling it.
Device disable is initiated by asserting the asynchronous DEV_OFF_N pin. The DEV_OFF_N pin has an
internal pull-up resistor, so that it can be left not connected to enable device operation.
While in device disable mode, the PCIe link is in L3 state. The PHY is in power down mode. Output
buffers are tri-stated.
Assertion or deassertion of PCIe PE_RST_N does not have any effect while the I210 is in device disable
mode (that is, the I210 stays in the respective mode as long as DEV_OFF_N is asserted). However, the
I210 might momentarily exit the device disable mode from the time PCIe PE_RST_N is de-asserted
again and until the Flash is read.
During power-up, the DEV_OFF_N pin is ignored until the NVM is read. From that point, the I210 might
enter device disable if DEV_OFF_N is asserted.