Data Sheet

Design Considerations—Ethernet Controller I210
825
• Physically group together all components associated with one clock trace to reduce trace length and
radiation.
• Isolate I/O signals from high-speed signals to minimize crosstalk, which can increase EMI emission
and susceptibility to EMI from other signals.
• Avoid routing high-speed LAN traces near other high-frequency signals associated with a video
controller, cache controller, processor, or other similar devices.
12.5.6.13 Traces for Decoupling Capacitors
Traces between decoupling and I/O filter capacitors should be as short and wide as practical. Long and
thin traces are more inductive and would reduce the intended effect of decoupling capacitors. Also for
similar reasons, traces to I/O signals and signal terminations should be as short as possible. Vias to the
decoupling capacitors should be sufficiently large in diameter to decrease series inductance.
12.5.6.14 Light Emitting Diodes for Designs Based on the I210
The I210 provides three programmable high-current push-pull (default active low) outputs to directly
drive LEDs for link activity and speed indication. Each LAN device provides an independent set of LED
outputs. Each of the four LED outputs can be individually configured to select the particular event,
state, or activity, which is indicated on that output. In addition, each LED can be individually configured
for output polarity, as well as for blinking versus non-blinking (steady-state) indication.
Since the LEDs are likely to be integral to a magnetics module, take care to route the LED traces away
from potential sources of EMI noise. In some cases, it might be desirable to attach filter capacitors.
The LED ports are fully programmable through the Flash interface.
12.5.7 Physical Layer Conformance Testing
Physical layer conformance testing (also known as IEEE testing) is a fundamental capability for all
companies with Ethernet LAN products. PHY testing is the final determination that a layout has been
performed successfully. If your company does not have the resources and equipment to perform these
tests, consider contracting the tests to an outside facility.
12.5.7.1 Conformance Tests for 10/100/1000 Mb/s Designs
Crucial tests are as follows, listed in priority order:
• Bit Error Rate (BER). Good indicator of real world network performance. Perform bit error rate
testing with long and short cables and many link partners. The test limit is 10
-11
errors.
• Output Amplitude, Rise and Fall Time (10/100 Mb/s), Symmetry and Droop (1 GbE). For the I210,
use the appropriate PHY test waveform.
• Return Loss. Indicator of proper impedance matching, measured through the RJ-45 connector back
toward the magnetics module.
• Jitter Test (10/100 Mb/s) or Unfiltered Jitter Test (1000 Mb/s). Indicator of clock recovery ability
(master and slave for a GbE controller).
12.5.8 Troubleshooting Common Physical Layout Issues
The following is a list of common physical layer design and layout mistakes in LAN On Motherboard
(LOM) designs.