Data Sheet

Ethernet Controller I210 —Design Considerations
822
12.5.6.5 Maximum Trace Lengths Based on Trace Geometry
Note:
1. Longer MDI trace lengths might be achievable, but might make it more difficult to achieve IEEE conformance. Simulations have
shown deviations are possible if traces are kept short. Longer traces are possible; use cost considerations and stack-up
tolerance for differential pairs to determine length requirements.
2. Deviations from 100 Ω nominal and/or tolerances greater than 15% decrease the maximum length for IEEE conformance.
Use the MDI differential trace calculator to determine the maximum MDI trace length for board-specific
trace geometry and board stack-up. Contact your Intel representative for access.
The following factors can limit the maximum MDI differential trace lengths for IEEE conformance:
• Dielectric thickness
• Dielectric constant
• Nominal differential trace impedance
• Trace impedance tolerance
• Copper trace losses
• Additional devices, such as switches, in the MDI path may impact IEEE conformance.
Board geometry should also be factored in when setting trace length.
Table 12-21. Maximum Trace Lengths Based on Trace Geometry and Board Stack-Up
Dielectric
Thickness
(mils)
Dielectric
Constant (DK)
at
1 MHz
Width /
Space/ Width
(mils)
Pair-to-Pair
Space (mils)
Nominal
Impedance (Ω)
Impedance
Tolerance (±%)
Maximum Trace
Length
(inches)
1
2.7 4.05 4/10/4 19 95
2
17
2
3.5
2.7 4.05 4/10/4 19 95
2
15
2
4
2.7 4.05 4/10/4 19 95 10 5
3.3 4.1 4.2/9/4.2 23 100
2
17
2
4
3.3 4.1 4.2/9/4.2 23 100 15 4.6
3.3 4.1 4.2/9/4.2 23 100 10 6
4 4.2 5/9/5 28 100
2
17
2
4.5
4 4.2 5/9/5 28 100 15 5.3
4 4.2 5/9/5 28 100 10 7
4 4.2 5/7/5 28 95 10 5.4
4 4.2 5/7/5 28 95 15 4.8
4 4.2 5/7/5 28 95 17 4.3