Data Sheet

Ethernet Controller I210 —Interconnects
82
Once the structure is loaded to the PHY, the EEMNGCTL.CFG_DONE bit is set.
3.4.2.4 iNVM Structure (Version Information)
• Bit 2:0 = Invalidated
• bit 4:3 = Reserved 0x1
• bit 8:5 = Reserved 0xF
• Bit 31:16 = Version number (number of 1' s show the version number 0x1 = 1, 0x3 =2, 0x7 =3,
etc.)
3.4.3 iNVM Programming Flows
iNVM can be programmed at several occasions and via different means:
1. At the chip manufacturing site (by Intel), via a special pin. It sets the critical PCIe settings required
by the I210 to show up correctly on the PCIe bus with a default device ID.
2. At customer premises (by OEMs), via an Intel provided software tool, which uses a special register
set. This tool enables customers to make some customization to the LEDs, device ID, ASPM, etc.
and it sets the per-controller settings.
For security reasons, the I210 has a lock-out mechanism after the iNVM is programmed at this
stage, to prevent any tampering/retry of the iNVM programming. It is activated by writing a special
iNVM word auto-load structure, iNVM word address 0xA, bit 15 set to 1b. The lock-out is active as
long as the SECURITY-EN strapping option is enabled.
3. By disabling the SECURITY_EN strapping option, the iNVM lines left blank become writable again
like in step 2. This can be useful for fixing iNVM values that were programmed wrongly, or, if boards
are resold to a third party who wants to further customize the iNVM. For example, the third party
might want a different MAC address or device ID to identify the device with their company's custom
software. At the end of this iNVM write cycle, the SECURITY_EN strapping option must be re-
enabled.
3.4.3.1 iNVM Programming Flow via Registers
Writing the iNVM via this flow must be done when the system is idle, with no Rx/Tx traffic running and
with PCIEMISC.DMA Idle Indication bit set to 1b. The iNVM memory is organized in 32 lines of 64 bits
each, for a total of 2 Kb.
1. To be sure the PHY clock used by iNVM programming logic gets stabilized, wait (at least) 15 s after
EEMNGCTL.CFG_DONE bit is read as 1b.
a. Skip this step on devices that have no attached Flash parts with a valid contents
2. To avoid mistakenly writing the iNVM, write the iNVM_PROTECT.CODE register field with
0xABACADA (ALLOW_WRITE bit is set to 1b).
3. Read the iNVM memory line to be programmed, use iNVM_DATA[2n] and iNVM_DATA[2n+1]
register (n=0,...,31), respectively for the lower and higher Dwords of the iNVM line to be
programmed.
4. Write the desired value in iNVM_DATA[2n].
5. Wait 320 s, which is the time required for a complete burning of the 32-bit fuses or poll
iNVM_PROTECT.BUSY until it is cleared.
6. Write the desired value in iNVM_DATA[2n+1].
7. Wait 320 s, which is the time required for a complete burning of the 32-bit fuses.