Data Sheet

Design Considerations—Ethernet Controller I210
805
12.0 Design Considerations
This section provides general design considerations and recommendations when selecting components
and connecting special pins to the I210. Intel recommends that these design considerations be used in
conjunction with the following board design documents:
•Intel
®
Ethernet Controller I210_82574 – Schematics / Diagrams
•Intel
®
Ethernet Controller I210-IS – Schematics / Diagrams
•Intel
®
Ethernet Controller I210-AT_I211-AT – Schematics / Diagrams
•Intel
®
Ethernet Controller I210_82574 – Dual Layout Review Checklist
•Intel
®
Ethernet Controller I210-IS – Layout Review Checklist
•Intel
®
Ethernet Controller I210-AT/IT – Layout Review Checklist
•Intel
®
82574_82583 Gigabit Ethernet Controller to I210_I211 – Design Guide
12.1 PCIe
12.1.1 Port Connection to the I210
PCIe is a dual simplex point-to-point serial differential low-voltage interconnect with a signaling bit rate
of 2.5 Gb/s per direction. The I210’s PCIe port consists of an integral group of transmitters and
receivers. The link between the PCIe ports of two devices is a x1 lane that also consists of a transmitter
and a receiver pair. Note that each signal is 8b/10b encoded with an embedded clock.
The PCIe topology consists of a transmitter (Tx) located on one device connected through a differential
pair connected to the receiver (Rx) on a second device. The I210 can be located on a LOM or on an
add-in card using a connector specified by PCIe.
The lane is AC-coupled between its corresponding transmitter and receiver. The AC-coupling capacitor
is located on the board close to transmitter side. Each end of the link is terminated on the die into
nominal 100 differential DC impedance. Board termination is not required.
For more information on PCIe, refer to the PCI Express* Base Specification, Revision 1.1, PCI Express*
Card Electromechanical Specification, Revision 1.1RD, and PCIe v2.1 (2.5GT/s) Gen1 x 1.
For information about the I210’s PCIe power management capabilities, see Section 5.0.
12.1.2 PCIe Reference Clock
The I210 uses a 100 MHz differential reference clock, denoted PECLKp and PECLKn. This signal is
typically generated on the system board and routed to the PCIe port. For add-in cards, the clock is
furnished at the PCIe connector.
The frequency tolerance for the PCIe reference clock is +/- 300 ppm.