Data Sheet

Electrical/Mechanical Specification—Ethernet Controller I210
799
11.6.2.9 PCIe Interface DC/AC Specification
The I210 PCIe Gen 1 interface supports the electrical specifications defined in:
• PCI Express* 2.0 Card Electro-Mechanical (CEM) Specification.
• PCI Express* 2.1 Base Specification, Chapter 4.
11.6.2.9.1 PCIe Specification - Input Clock
The input clock for PCIe must be a differential input clock in frequency of 100 MHz. For full
specifications please check the PCI Express* 2.0 Card Electro-Mechanical (CEM) Specification (refclk
specifications for Gen 1).
11.6.3 SerDes DC/AC Specification
The SerDes interface supports the following standards:
1. PICMG 3.1 specification Rev 1.0 1000BASE-BX.
2. 1000BASE-KX electrical specification defined IEEE802.3ap clause 70.
3. SGMII on 1000BASE-BX or 1000BASE-KX compliant electrical interface (AC coupling with internal
clock recovery).
4. SFP (Small Form factor Pluggable) Transceiver Rev 1.0
11.6.4 PHY Specification
The specifications define the interface for the back-plane board connection, interface to external
1000BASE-T PHY and the interface to fiber or SFP module.
DC/AC specification is according to Standard 802.3 and 802.3ab version 2008.
100 Base-T parameters are also described in standard ANSI X3.263.
11.6.5 XTAL/Clock Specification
The 25 MHz reference clock of the I210 can be supplied either from a crystal or from an external
oscillator. The recommended solution is to use a crystal.
11.6.5.1 Crystal Specification
Table 11-15. Specification for External Crystal
Parameter Name Symbol Recommended Value Conditions
Frequency f
o
25.000 [MHz] @25 [°C]
Vibration mode Fundamental
Cut AT
Operating /Calibration Mode Parallel
Frequency Tolerance @25°C f/f
o
@25°C ±30 [ppm] @25 [°C]
Temperature Tolerance f/f
o
±30 [ppm]