Data Sheet

Electrical/Mechanical Specification—Ethernet Controller I210
791
11.6.2 Digital I/F AC Specifications
11.6.2.1 Reset Signals
The timing between the power up sequence and the different reset signals is described in Figure 11-1
and in Table 11-2.
11.6.2.1.1 LAN_PWR_GOOD
The I210 uses an internal power on detection circuit in order to generate the LAN_PWR_GOOD signal.
Reset can also be implemented when the external power on detection circuit determines that the device
is powered up and asserts the LAN_PWR_GOOD signal to reset the device.
11.6.2.2 SMBus
Table 11-8 lists the timing guaranteed when the driver or the agent is performing the action. Where
only a typical value is specified, the actual value will be within 2% of the value indicated.
VOH
2
Output High Voltage IOH = -4 mA; VCC3P3 = Min
VCC3P3 -
0.4
V
VOL Output Low Voltage IOL = 4 mA; VCC3P3 = Min 0.4 V
VIH Input High Voltage
0.7 x
VCC3P3
V
VIL Input Low Voltage
0.3 x
VCC3P3
V
Vihyst Input Hysteresis 100 mV
Iil/Iih Input Current VCC3P3 = Max; Vin =3.6V/GND 20 µA
Cin Input Capacitance 5pF
1. Applies to the NC_SI_CLK_OUT, NC_SI_CRS_DV, NC_SI_RXD[1:0], NC_SI_ARB_OUT, NC_SI_TX_EN, NC_SI_TXD[1:0],
NC_SI_CLK_IN, NC_SI_ARB_IN.
2. NC_SI_ARB_OUT - VOH Min = VCC3P3-0.65 [V].
Table 11-8. SMBus Timing Parameters (Master Mode)
Symbol Parameter Min
Typ 100
Khz
Typ 400
Khz
Typ 1
MHz
Max Units
F
SMB
SMBus Frequency 100 400 1000 1000 kHz
T
BUF
Time between Stop and Start
condition driven by the I210
0.5 4.7 1.3 0.5 µs
T
HD:STA
Hold Time After Start Condition.
After this period, the first clock is
generated.
0.26 4 0.6 0.26 µs
T
SU:STA
Start Condition Setup Time 0.14 2 0.3 0.14 µs
T
SU:STO
Stop Condition Setup Time 0.26 4 0.6 0.26 µs
T
HD:DAT
Data Hold Time 00.300 µs
T
SU:DAT
Data Setup Time 0.05 0.25 0.1 0.05 µs
Table 11-7. NC-SI Pads DC Specifications (Continued)
Symbol Parameter Conditions Min Max Units