Data Sheet

Ethernet Controller I210 —System Manageability
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10.8.2 Host Slave Command Interface to Manageability
This interface is used by the software device driver for several of the commands and for delivering
various types of data in both directions (Manageability-to-Host and Host-to-Manageability).
The address space is separated into two areas:
• Direct access to the internal data RAM: The internal shared (between Firmware and Software) RAM
is mapped to address space 0x8800 to 0x8EFF. Writing/reading to this address space goes directly
to the RAM.
• Control register located at address 0x8F00.
10.8.2.1 Host Slave Command Interface Low Level Flow
This interface is used for the external host software to access the manageability subsystem. Host
software writes a command block or read data structure directly from the data RAM. Host software
controls these transactions through a slave access to the control register.
The following flow shows the process of initiating a command to the manageability block:
1. The Software clears the FWSTS.FWRI flag (clear by write one) to car any previous firmware reset
indications.
2. The Software device driver takes ownership of the Management Host interface using the flow
described in Section 4.6.1.
3. The Software device driver reads the HOST Interface Control Register (See Section 8.23.2) and
checks that the Enable (HICR.En) bit is set.
4. The Software device driver writes the relevant command block into the RAM area that is mapped to
addresses 0x8800-0x8EFF.
5. The Software device driver sets the Command (HICR.C) bit in the HOST Interface Control Register
(See Section 8.23.2). Setting this bit causes an interrupt to the ARC (can be masked).
6. The Software checks the FWSTS.FWRI flag to make sure a firmware reset didn’t occur during the
command processing. If this bit is set, the command may have failed.
7. The Software device driver polls the HOST Interface Control register for the Command (HICR.C) bit
to be cleared by Firmware.
8. When Firmware finishes with the command, it clears the Command (HICR.C) bit (if Firmware replies
with data, it should clear the bit only after the data is placed in the shared RAM area where the
software device driver can read it).
If the Software device driver reads the HOST Interface Control register and the HICR.SV bit is set to 1b,
then there is a valid status of the last command in the shared RAM. If the HICR.SV bit is not set, then
the command has failed with no status in the RAM.
On completion of access to the shared RAM Software device driver should release ownership of the
shared RAM using the flow described in Section 4.6.2.
10.8.2.2 Host Slave Command Registers
10.8.2.2.1 Host Interface Control Register (CSR Address 0x8F00)
This register operates along with the host software/firmware interface (See Section 8.23.1).