Data Sheet

Ethernet Controller I210 —Interconnects
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6. Release the Flash semaphore.
a. Software must avoid taking the Flash semaphore again until the firmware resets and reloads
from the new image. Any new attempt to write the Flash until then is not performed by the
device.
7. If the NVM_SEC_EN bit is read as 0b (bit 13 in Flash word 0x12) or if the security-disable strapping
pin is set, then firmware enters the device in the non-secured mode.
8. Firmware swaps between the Free Provisioning Area Pointer (word 0x40) and the Firmware Secured
Module pointer located at the shadow RAM word address 0x10, and updates the SW Checksum at
word 0x3FFirmware dumps the shadow RAM into the Flash.Software polls the FLFWUPDATE.AUTH-
DONE bit until it is read as 1b.
a. If FLFWUPDATE.AUT_FAIL bit is read as 1b, it means that the update process failed because of
one of the security checks has failed or because of some defect in the Flash write. In such case
software exits the flow and might decide to rerun it from the beginning.
Note: The device may not reply to requests from the MC during the firmware update process, which
can last up to 3 seconds.
3.3.9.3 VPD Write Flows
3.3.9.3.1 First VPD Area Programming
The VPD capability is exposed on the PCIe interface only if the VPD_EN bit in Flash word 0x0A is set to
1b, regardless of any other sanity check that is performed on the VPD area contents.
The VPD contents and pointer can be written on a blank Flash without any limitation, similar to any
other Flash module when in the blank Flash programming mode. This is the recommended way to map
the VPD area into the RO protected area of the shadow RAM, which is highly advised.
3.3.9.3.2 VPD Area Update Flow
1. The host performs a VPD write - it sets write offset/data into VPD register set of the configuration
space, setting the VPD Flag (bit 15 in VPD Address Register - 0x0E2).
2. Firmware checks the VPD write is allowed - it checks that the write offset points to the VPD-RW
area and not to the RO area of the shadow RAM and nor to the VPD-RO area.
a. If it is not, firmware clears the VPD flag in the configuration space to notify the VPD software
that the transaction completed, and exits the flow.
3. Firmware takes Flash semaphore ownership.
4. Firmware re-starts the 10 ms VPD timer and writes the change into shadow RAM.
5. Firmware completes the VPD access to software - firmware clears the VPD flag in the configuration
space to notify the VPD software that the access completed.
6. Firmware releases Flash semaphore ownership.
7. When the VPD timer expires, firmware dumps the shadow RAM into the Flash.
If VPD write access is attempted by the host when the device has just started a Flash erase
operation, or if Flash ownership is held by software for a long time, then the VPD write
request might time out as the firmware code responsible to handle the request would not be
readable from the Flash. As a result, Intel recommends that a software application that
modifies the VPD area perform back-to-back VPD write accesses within no longer than 10 ms
between two consecutive writes.