Data Sheet

Interconnects—Ethernet Controller I210

• If the I210 does not detect a value of 0x82 in the first byte of the VPD area or if no End tag is

detected, or if the structure does not follow the description of Table 3.17, it assumes the area is not

programmed:

— Any read/write access through the VPD registers set are ignored.

— The VPD pointer itself remains RO.

• The VPD RO area and RW area are both optional and can appear in any order. A single area is

supported per tag type. Refer to Appendix I in the PCI 3.0 specification for details of the different

tags.

• If a VPD-W tag is found, the area defined by its size is writable via the VPD structure.

• The VPD must be accessed through the PCIe configuration space VPD capability structure listed in

Table 3.17. Write accesses to a read only area or any accesses outside of the VPD area via this

structure are ignored. The VPD area is also accessible for read via the EEPROM-mode access, and

for write via the same access mode - only if the VPD area is mapped to a RW area of the shadow

RAM (not recommended).

• VPD area must be mapped to the first valid 4 KB sector of the Flash.

VPD software does not check the semaphores before attempting to access the Flash via dedicated VPD

registers. Even if the Flash is owned by another entity, VPD software read or write access directed to

the VPD area might complete immediately since it is first performed against the shadow RAM. Firmware

is responsible for handling the VPD read and write accesses against the host. Hardware notifies

firmware each time a VPD access was initiated. However, VPD software write access is written into the

Flash device at the firmware’s initiative, which might take up to several seconds. Refer to

Section 3.3.9.3.

3.3.9 Flash Structure and Update Flows

3.3.9.1 Flash Organization

The I210 Flash contains the following three high-level modules:

• Legacy EEPROM Modules. These modules correspond to the legacy EEPROM contents, they are

mapped to one of the first two 4 KB sectors of the Flash device, and cannot be extended beyond

these sectors. They are composed of all the Flash modules used by the hardware (such as PCIe

down to MAC blocks, PHYs excluded) or ones used by the manageability firmware. In prevision to

the RO Updates structure 3 (refer to Section 6.9.2.2), the last 4 words of the shadow RAM must

always be left unused, filled with all 1s contents.

• Expansion/Option ROM Module. Must fit within 512 KB and shall start at the fixed word address

0x1000. It includes the PXE driver (61 KB), iSCSI boot image (116 KB), FCoE boot image (80 KB),

UEFI network driver (37 KB for x64, 67 KB for IA64), and can also include a CLP module (60 KB).

Refer to Section 3.3.3.1.

• Secured Area (Firmware Secured Module). Must fit within 244 KB (or 448 KB) and start at a 4

KB boundary. It is mainly destined to store firmware code, but it can also include other firmware

structures and modules. It is pointed from the Flash word address 0x10, in either sector 0 or 1.

• Free Provisioning Area. This area is 244 KB (or 448 KB) in size. Following a firmware update

event, it becomes the new secured area and the old secured area becomes the new free

provisioning area. It is pointed from the NVM word address 0x40, in either sector 0 or 1.

• mDNS Records. This module contains the mDNS records used by the firmware for mDNS offload

proxy while the system is in D3. The module must be mapped next to the secured area. The size

provisioned for mDNS records is 16 KB. The module’s offset from the beginning of the secured area

is given by NVM word 0x25, in either sector 0 or 1.

Notes: Flash device size can be read by host from FLA.FL_SIZE register field.