Data Sheet

Interconnects—Ethernet Controller I210

10. FLSWCTL.GLDONE bit is set by hardware when the last byte programmed has been written. But

software can stop the transaction in the middle as long as it got the DONE bit read as 1b. In any

case, the FLBUSY bit must be read as 0b before releasing the Flash semaphore.

3.3.5.6 Software Flash Read Flow via the Flash-Mode Interface

The I210 provides an engine for reading the Flash in a burst mode:

1. Poll the FLSWCTL.DONE bit until it is set. This step is only needed if the flow is executed following a

reset event.

2. Set the FLSWCNT.CNT field with the number of bytes to be read from Flash in a burst mode.

3. Set the FLSWCTL.ADDR field with the byte address of the first Dword to be read and set the CMD

field to 0000b. The FLSWCTL.GLDONE bit is cleared by hardware to indicate a burst read has

started.

4. Hardware starts accessing the Flash and clears the FLSWCTL.DONE bit until it writes the read

Dword into the FLSWDATA register.

5. Software polls the FLSWCTL.DONE bit until it is set.

6. Software reads the Dword from FLSWDATA register, which is used by hardware to trigger a clear of

the FLSWCTL.DONE bit again.

7. Hardware increments FLSWCTL.ADDR field by four (Dword granularity) if byte count left is greater

or equal to 4.

8. Steps 5 to 7 are repeated until the number of bytes programmed in FLSWCNT.CNT has been read.

9. Hardware sets the FLSWCTL.GLDONE bit to indicate that all the Flash transactions related to the

command issued at step 3 were completed. However, software can stop the transaction in the

middle as long as it got the DONE bit set.

3.3.6 Flash Validity Field

The only way the I210 can tell if a Flash is present and programmed is by trying to read the Flash

Validity field at Flash word addresses 0x012 and 0x812. If one of the Validity fields is read as 01b, a

programmed lash is assumed to be present.

3.3.7 Flash Deadlock Avoidance

The Flash is a shared resource between the following clients:

1. Hardware auto-read.

2. LAN software accesses.

3. Manageability accesses.

4. Software tools.

All clients can access the Flash using parallel access, on which hardware implements the actual access

to the Flash. Hardware schedules these accesses, avoiding starvation of any client.

However, the software and firmware clients can access the Flash using bit-banging. In this case, there

is a request/grant mechanism that locks the Flash to the exclusive use of one client. If one client is

stuck without releasing the lock, the other clients can no longer access the Flash. To avoid this

deadlock, the I210 implements a timeout mechanism, which releases the grant from a client that holds

the Flash bit-bang interface (FLA.FL_SCK bit) for more than 8 seconds. If any client fails to release the

Flash interface, hardware clears its grant enabling the other clients to use the interface.

Note: The bit-banging interface does not guarantee fairness between the clients, therefore it should

be avoided in normal operation as much as possible. When write accesses to the Flash are