Data Sheet

Ethernet Controller I210 —Interconnects
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As a response, hardware executes the following steps:
1. Eventually clears the CMDV bit if the command cannot be currently executed, and goes to step 3.
2. The I210 writes the data to the shadow RAM.
3. The I210 sets the DONE bit in the EEWR register.
Notes: The VPD area of the Flash can be accessed only via the PCIe VPD capability structure.
EEPROM-mode writes are performed into the internal shadow RAM. Software can instruct
copying of the internal shadow RAM content into the base sector of the Flash device by
setting the EEC.FLUPD bit.
3.3.5.4 Flash Program Flow via the Memory Mapped Interface
Software must take semaphore ownership before executing the flow. Software initiates a write cycle via
the Flash BAR as follows:
1. Write the data byte to the Flash through the Flash BAR. Use the Byte Enable (BE) pins if less than
four bytes has to be written.
2. Poll the FL_BAR_BUSY flag in the FLA register until cleared.
3. Repeat the steps 1 and 2 if multiple bytes should be programmed.
As a response, hardware executes the following steps for each write access:
1. Set the FL_BAR_BUSY bit in the FLA register.
2. Initiate autonomous write enable instruction.
3. Initiate the program instruction right after the enable instruction.
4. Poll the Flash status until programming completes.
5. Clear the FL_BAR_BUSY bit in the FLA register.
Note: Software must erase the sector prior to programming it.
3.3.5.5 Software Flash Program Flow via the Flash-Mode Interface
Software must take semaphore ownership before executing the flow.
1. Poll the FLSWCTL.DONE bit until it is set. This step is only needed if the flow is executed following a
reset event.
2. Write the number of bytes to be written into FLSWCNT.CNT field. The write must not cross a page
(256 byte) boundary.
3. Set the ADDR field with the byte resolution address in the FLSWCTL register and set the CMD field
to 0001b.
4. Write the data to the FLSWDATA register.
5. Hardware starts accessing the Flash and begins writing data bits from the FLSWDATA register. If the
write is not allowed, the CMDV bit is cleared instead.
6. Once hardware completes writing the data to the Flash, the FLSWCTL.DONE register bit is set.
7. Hardware increments FLSWCTL.ADDR field by four (Dword granularity) if byte count left is greater
or equal to 4.
8. Software polls the FLSWCTL.DONE bit until it is set.
9. Steps 4 to 8 are repeated several times until the number of bytes programmed in FLSWCNT.CNT
field has been written.