Data Sheet

Interconnects—Ethernet Controller I210
67
1. Write a 1b to the Flash Request bit (FLA.FL_REQ).
2. Read the Flash Grant bit (FLA.FL_GNT) until it becomes 1b. It remains 0b as long as there are other
accesses to the Flash.
3. Write or read the Flash using the direct access to the 4-wire interface as defined in the FLA register.
The exact protocol used depends on the Flash placed on the board and can be found in the
appropriate datasheet.
4. Write a 0b to the Flash Request bit (FLA.FL_REQ).
5. Following a write or erase instruction, software should clear the Request bit only after it has
checked that the cycles were completed by the Flash. This can be checked by reading the BUSY bit
in the Flash device Status register. Refer to Flash datasheet for the OpCode to be used for reading
the Status register.
Notes: The bit-banging interface is not expected to be used during normal operation. Software
should instead use the EEPROM-mode when accessing the base sector and the Flash-mode
for other sectors.
If software must use the bit-banging interface in normal operation, it should adhere to the
following rules:
• Gain access first to the Flash using the firmware/software semaphore mechanism.
• Minimize the FLA.FL_REQ setting for a single byte/word/Dword access or other method
that guarantee fast enough release of the FLA.FL_REQ.
When hardware Flash bit-bang access is aborted due to deadlock avoidance, the
FLA.FLA_ABORT bit is set. To clear the block condition and enable further access to the Flash,
software should write 1b to the FLA.FLA_CLR_ERR bit.
3.3.5.3 Software Word Program Flow to the EEPROM-Mode Interface
Software must take semaphore ownership before executing these flows.
3.3.5.3.1 Read Interface
Software initiates a read cycle to the Flash via the EEPROM-mode as follows:
1. Software writes the address to be read in the EERD register
2. Software polls the EERD.DONE bit until it is asserted.
3. Software reads the EERD.DATA register field.
Hardware executes the following steps:
1. Eventually clears the CMDV bit if the command cannot be currently executed, and goes to step 4.
2. Reads the data from the shadow RAM.
3. Puts the data in DATA field of the EERD register.
4. Sets the DONE bit in the EERD register.
Note: Any word read this way is not loaded into the I210's internal registers. This happens only at a
hardware auto-load event.
3.3.5.3.2 Write Interface
Software initiates a write cycle to the Flash via the EEPROM-mode as follows:
1. Poll the DONE bit in the EEWR register until it is set.
2. Write the data word and its address in the EEWR register.