Data Sheet

Ethernet Controller I210 —Interconnects
66
3.3.5 Flash Read, Write, and Erase Sequences
Note: This section describes the low-level Flash procedures handled between software, firmware,
and hardware. The high-level Flash flows are built using these procedures, and include the
semaphore taking/releasing and other high level tasks. Refer to Section 3.3.11.Each time
programming the NVM via CSR accesses, PCIEMISC.DMA Idle Indication bit must be set to
1b.
3.3.5.1 Flash Erase Flow by Software
In this section, software uses FLSW* registers.
Device Erase Flow:
1. Poll the FLSWCTL.DONE bit until it is set.
2. Set FLSWCTL.CMD fields to 0011b.
3. Wait until FLSWCTL.DONE bit is read as 1b and FLSWCTL.FLBUSY bit is read as 0b before releasing
the Flash semaphore.
Hardware sets the DONE bit without executing the operation if software attempts this command while
in Flash secure mode. The CMDV field is cleared in such case.
Sector Erase Flow:
1. Poll the FLSWCTL.DONE bit until it is set.
2. Set FLSWCTL.CMD field to 0010b and set the FLSWCTL.ADDR field to any address that belongs to
the Flash 4 KB sector to be erased.
3. Wait until the FLSWCTL.DONE bit is read as 1b and the FLSWCTL.FLBUSY bit is read as 0b before
releasing the Flash semaphore.
Hardware sets the DONE bit without executing the operation if software attempts to erase a protected
sector while in Flash secure mode. The CMDV field is cleared in such case.
3.3.5.2 Software Flow to the Bit-banging Interface
This section is relevant to software only while in the non-secure mode.
To directly access the Flash, software should follow these steps:
PCIe to SMBus switching in MCTP mode Ignored
SMBus to PCIe switching in MCTP mode Ignored
NC-SI packet received
Command completed with
Package Not Ready error
code.
Command validity checks are not performed.
Packets received do not increment the NC-SI
statistics counters.
Note: The command is answered even if
the package was previously un-
selected.
Any event that requires issuing an AEN Ignored
All relevant events are processed right after
Flash access is recovered.
Command received in the host interface Ignored
Commands are processed right after Flash
access is recovered.
SMBus ARP offload
SMBus ARP offload is
performed
New SMBus addresses are written to the Flash
right after Flash access is recovered.
VPD write command received Ignored
The VPD write is processed (and F bit set)
right after Flash access is recovered.
Event Response Comment