Data Sheet

ManualsBrandsIntel ManualsComputing & OfficeIntel Intel Ethernet Server Adapter I210-T1 - Network adapter 1 Gbps LAN (10/100/1000 Mbps), PCI-Express

Interconnects—Ethernet Controller I210

Cache reads can be delayed by the maximum time duration (300 ms) of a previous erase

command, which was issued by firmware to hardware. Before issuing any sector erase command to

hardware, firmware must complete all its pending tasks and must load from Flash the code pieces

required to manage while the Flash is busy for erasing:

a. For instance, NC-SI commands received are completed with the Package Not Ready status. The

MC must retry after 500 ms the commands that were completed with a Package Not Ready

status. SMBus transactions are handled in a similar way. Refer to Section 3.3.4.2 for the

complete list.

b. Offloads performed by firmware waits until the cache read resumes before being handled by

firmware. Alternatively, before issuing an Erase command to hardware, firmware initiates some

offload tasks that would timeout otherwise.

c. Host interface commands can wait for 500 ms before being completed by firmware.

3. Software or firmware read is performed by hardware in a round robin manner between:

a. Software reads via BAR or CSRs - Software other than BIOS must take a semaphore (even for

reads).

b. Firmware reads via CSRs - no semaphore taking. Firmware is also performing the shadow RAM

reads required for a VPD read.

4. Firmware erase/write for VPD and the MC, before performing a shadow RAM dump into the Flash, or

for its own needs (such as for replacing factory defaults), firmware must take the semaphore here.

5. Software erase/write via BAR or CSRs - Software must take a semaphore.

a. If the access is performed against the Flash, software must release the semaphore after it has

checked the Flash is not busy by the last erase operation performed.

b. If the access is performed against the shadow RAM, software must release the semaphore once

it has asked firmware to dump the shadow RAM in the Flash by setting the FLUPD bit.

6. Bit-banging access - no semaphore taking.

This access is provided to software only when in non-secure mode.Firmware access via the bit-

banging interface might lead to a dead lock if the firmware code required to complete the bit-

banging is not entirely in the firmware cache before starting the access.

3.3.4.2 Firmware Responses When Flash Unavailable

Table 3-14 is organized according to the different events that might occur while the Flash is temporarily

not available (like busy with a pervious Flash erase operation). It defines the expected responses for

each case, assuming the firmware code, which is responsible to properly handle the event cannot be

read from the Flash.

Table 3-14. Events/Responses When Flash is Unavailable

Event Response Comment

NetProxy packet received Ignored

Packets or timeouts are processed right after

Flash access is recovered.

MCTP packet received

A response with

ERROR_NOT_READY

(0x04) completion

code is returned.

SMBus read transaction

Not ready command

replied

SMBus write transaction

Byte count word is

NACKed

However, the address and the command are

acknowledged.