Data Sheet

System Manageability—Ethernet Controller I210
629
10.2 Components of the Sideband Interface
There are two components to a sideband interface:
•Physical Layer
•Logical Layer
The MC and the I210 must be in alignment for both components. An example issue: the NC-SI physical
interface is based on the NC-SI interface, but there are differences between the devices at the physical
level and the protocol layer is completely different.
10.2.1 Physical Layer
This is the electrical connection between the I210 and MC.
10.2.1.1 SMBus
The SMBus physical layer is defined by the SMBus specification. The interface is made up of two
connections: Data and Clock. There is also an optional third connection: the Alert line. This line is used
by the I210 to notify the MC that there is data available for reading. Refer to the SMBus specification for
details.
The SMBus can run at three speeds: 100 KHz (standard SMBus), 400 KHz (I
2
C fast mode) or 1 MHz
(I
2
C fast mode plus). The speed used is selected by the SMBus Connection Speed in SMBus Notification
Timeout and Flags Flash word.
10.2.1.1.1 PEC Support
SMBus transactions can be protected by using Packet Error Code (PEC). Packet Error Checking,
whenever applicable, is implemented by appending a PEC byte at the end of each message transfer.
The PEC byte is a CRC8 calculation on all the message bytes.
PEC is added in transmit and expected in receive for the following SMBus packets:
•ARP packets
• MCTP over SMBus transactions.
For ARA cycles and legacy SMBus transactions, a PEC is not expected.
The following table describes the behavior of the device in each PEC configured mode for transactions
directly handled by the hardware upon reception of packets with or without PEC.
Table 10-1. SMBus PEC Modes
1
Target PEC Mode
SMBus transaction
(relative to the I210)
I210 PEC Mode PEC Enabled PEC Disabled
Master Write
2
Enabled
(A) Target will ack the PEC
byte
(A) Target will nack the PEC
byte
Master Write
2
Disabled
(A) Target will receive stop
before expected PEC byte
(A) PEC byte is not expected
Slave Write
3
Enabled
(A) Target will ack last data
byte; PEC byte will be nacked
(A) Target will nack last data
byte; No PEC byte will be
written by Slave