Data Sheet

Ethernet Controller I210 —PCIe Programming Interface
624
9.5.3.4 TPH Steering Table (0x1AC - 0x1B8; R/W)
9.5.4 Latency Tolerance Requirement Reporting (LTR) Capability
The PCI Express Latency Tolerance Requirement Reporting Capability is an optional Extended Capability
that allows software to provide platform latency information to devices with upstream ports (Endpoints
and Switches). This capability structure is required if the device supports Latency Tolerance
Requirement Reporting (LTR).
The following table lists the PCIe LTR extended capability structure for PCIe devices.
Bit
Location
Attribute
Default
Value
Description
7:0 RW 0x0 Steering Table Lower Entry 2*n (n = 0...3). A value of zero indicates the tag is not valid
15:8 RO 0x0
Steering Table Upper Entry 2*n (n = 0...3) - RO zero in the I210, as extended tags are not
supported.
23:16 RW 0x0 Steering Table Entry 2*n + 1 (n = 0...3) - A value of zero indicates the tag is not valid
31:24 RO 0x0
Steering Table Upper Entry 2*n + 1 (n = 0...3) - RO zero in the I210, as extended tags are not
supported.
Byte Offset Byte 3 Byte 2 Byte 1 Byte 0
0x1C0
Next Capability Ptr.
(0x000)
Version (0x1) LTR Capability ID (0x18)
0x1C4
Maximum Non-Snooped Platform Latency
Tolerance Register
Maximum Snooped Platform Latency Tolerance
Register