Data Sheet

PCIe Programming Interface—Ethernet Controller I210
619
9.5.1.7 Advanced Error Capabilities and Control Register (0x118; RWS)
9.5.1.8 Header Log (0x11C:0x128; RO)
The Header Log register captures the header for the transaction that generated an error. This register
is 16 bytes in length.
14 RO 0b
Corrected Internal Error Mask (Optional)
Not supported in the I210.
15 RO 0b
Header Log Overflow Mask (Optional)
Not supported in the I210.
31:16 RO 0x0 Reserved
Bit
Location
Attribute
Default
Value
Description
4:0 ROS 0x0
First Error Pointer
The First Error Pointer is a field that identifies the bit position of the first error
reported in the Uncorrectable Error Status register.
5RO1b
ECRC Generation Capable
This bit indicates that the I210 is capable of generating ECRC.
This bit is loaded from Flash PCIe Control 2 word (Word 0x28).
6RWS0b
ECRC Generation Enable
When set, enables ECRC generation.
7RO1b
ECRC Check Capable
If Set, this bit indicates that the Function is capable of checking ECRC.
This bit is loaded from Flash PCIe Control 2 word (Word 0x28).
8 RWS 0b
ECRC Check Enable
When set, enables ECRC checking.
9RO0b
Multiple Header Recording Capable – If Set, this bit indicates that the Function is capable of
recording more than one error header.
10 RO 0b This bit enables the Function to record more than one error header.
11 RO 0b
TLP Prefix Log Present
If Set and the First Error Pointer is valid, indicates that the TLP Prefix Log register contains
valid information. If Clear or if First Error Pointer is invalid, the TLP Prefix Log register is
undefined.
Default value of this bit is 0b. This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear.
31:12 RO 0x0 Reserved
Bit
Location
Attribute
Default
Value
Description
127:0 ROS 0b Header of the packet in error (TLP or DLLP).
Bit
Location
Attribute
Default
Value
Description