Data Sheet

Ethernet Controller I210 —PCIe Programming Interface
618
9.5.1.5 Correctable Error Status (0x110; R/W1CS)
The Correctable Error Status register reports error status of individual correctable error sources on a
PCIe device. When an individual error status bit is set to 1b, it indicates that a particular error occurred;
software can clear an error status by writing a 1b to the respective bit.
9.5.1.6 Correctable Error Mask (0x114; RWS)
The Correctable Error Mask register controls reporting of individual correctable errors by device to the
host bridge via a PCIe error message. A masked error (respective bit set in mask register) is not
reported to the host bridge by an individual device. There is a mask bit per bit in the Correctable Error
Status register.
24 RO 0b
AtomicOps Egress Blocked Severity (Optional)
Not supported in the I210.
25 RO 0b
TLP Prefix Blocked Error Severity (Optional)
Not supported in the I210.
31:26 RO 0x0 Reserved
Bit
Location
Attribute
Default
Value
Description
0 R/W1CS 0b Receiver Error Status
5:1 RO 0x0 Reserved
6 R/W1CS 0b Bad TLP Status
7 R/W1CS 0b Bad DLLP Status
8 R/W1CS 0b REPLAY_NUM Rollover Status
11:9 RO 000 Reserved
12 R/W1CS 0b Replay Timer Timeout Status
13 R/W1CS 0b Advisory Non-Fatal Error Status
14 RO 0b
Corrected Internal Error Status (Optional)
Not supported in the I210.
15 RO 0b
Header Log Overflow Status (Optional)
Not supported in the I210.
31:16 RO 0x0 Reserved
Bit
Location
Attribute
Default
Value
Description
0 RWS 0b Receiver Error Mask
5:1 RO 0x0 Reserved
6RWS0bBad TLP Mask
7 RWS 0b Bad DLLP Mask
8 RWS 0b REPLAY_NUM Rollover Mask
11:9 RO 000b Reserved
12 RWS 0b Replay Timer Timeout Mask
13 RWS 1b
Advisory Non-Fatal Error Mask.
This bit is Set by default to enable compatibility with software that
does not comprehend Role-Based Error Reporting.
Bit
Location
Attribute
Default
Value
Description